trendforce.com, Apr. 18, 2025 –
RIVAI Launched China’s First Fully Self-Developed High- Performance RISC-V Server Chip
Recently, RIVAI officially unveiled its next-generation high-performance processor, Lingyu, in Qianhai, Shenzhen. As China’s first fully self-developed high-performance RISC-V server chip, Lingyu is up to international mainstream standards in computing power, energy efficiency, and interface configuration, making it suitable for scenarios such as high-performance computing (HPC), all-flash storage, and large open-source language models like DeepSeek.
Lingyu processor is built on RIVAI’s independently developed CPU core IP and on-chip network IP, achieving advanced out-of-order execution, high-speed data paths, and a mesh interconnect architecture. Through a co-optimization approach combining hardware-software co-design and process design, the chip introduces innovations across product engineering, EDA toolchain, physical design, and wafer manufacturing processes, significantly improving energy efficiency and reducing total cost of ownership (TCO).
Lingyu’s computing performance is said to rival mainstream server chips from Intel and AMD, signaling RISC-V’s entry into the high-performance era. In terms of memory and I/O support, Lingyu supports DDR5 high-speed memory, PCIe 5.0 standard, CXL 2.0 protocol, and up to 8-way interconnects. It also boasts enterprise-grade RAS (Reliability, Availability, and Serviceability) features, aligning with RISC-V server standards. The processor integrates a dedicated management core and supports dynamic tuning to ensure stability under high workloads, meeting the demands of enterprise data centers.
Up till now, Lingyu’s ecosystem already includes over 50 partners, covering key component suppliers, OEMs, system software vendors, and industry solution providers.
World’s First 32-bit RISC-V Microprocessor Based on 2D Semiconductor Materials Debuts
In April, Fudan University announced that a team led by Zhou Peng and Bao Wenzhong from the National Key Laboratory of Integrated Circuits and Systems successfully developed WUJI, the world’s first 32-bit RISC-V microprocessor based on a 2D semiconductor material—molybdenum disulfide (MoS₂). The research result was published in Nature on the evening of April 2 (Beijing time).
The chip integrates 5,900 transistors using a uniquely developed integration process and the open-source RISC-V instruction set architecture, setting a new international record for the largest-scale verification of a 2D logic chip.
Han Jun, a researcher at the School of Microelectronics, was responsible for the RISC-V architecture design. He explained that choosing this architecture means that future ecosystem, which aligns with global technology standards while avoiding reliance on closed architectures, can be developed independently free from dependence on foreign vendors’ architectures and IP patents.
Nuclei System Technology and Silergy Demonstrated Automotive RISC-V Chip
Recently, Nuclei System demonstrated the successful application of its high-performance NA900 series RISC-V processor IP in Silergy’s SA32D automotive MCU series.
Nuclei noted that the SA32D MCU, which uses its six-core NA900 RISC-V CPU IP, has achieved several industry breakthroughs:
Performance: The SA32D MCU, fitted with NA900 IP, delivers 4.6K DMIPS at 300MHz, significantly outperforming Cortex-R5 and R52-based MCUs in Dhrystone and Coremark benchmarks.