Industry Articles

Most SoC designs have some typical characteristics, including multiple IP import and reuse of both hard and soft IP, as well as large, chip-wide buses that route the signals and clocks across the many millimeters of silicon space. The challenges begin when the scaling of the process te chnology — to 90 nanometers and beyond — leads to natural frequency increases to 1 GHz and beyond. This in turn can cause even the lowest frequencies on the SoC to be in the gigahertz range. At this point, a plethora of signal integrity issues arise, which are in themselves complex to understand, very difficult to model and almost impossible to eliminate. Among the most problematic are:

Interconnect crosstalk. This is usually due to the capacitive coupling between the victim net and one or more aggressor net, although inductive coupling is also beginning to show up in cutting-edge custom designs. The problem of interconnect crosstalk is getting worse with each process generation due to nonideal scaling of wires. Since wires grow relatively narrower and taller with each generation (in order to keep their resistance manageable), the ratio of the coupling capacitance of a wire to its total capacitance is increasing with each generation. Although the move from aluminum to copper can halt this deterioration for a generation, successive generations will again have to tackle the same issues. Therefore, it is becoming increasingly important for the designer to account for coupling during timing analysis.

• Increasing design size and power consumption and decreasing supply voltage — thus, increasing current. The result is an increase in the amount of power grid IR drop and ground bounce on chips. This trend is critical as the IR drop and ground bounce noise margins are decreasing along with the supply voltage. Chip failures due to power grid issues, whether IR drop or electromigration, are already being discovered by chip designers. Since these issues are related to the number of components and the way they are assembled on a chip — primarily a global phenomenon — power grid analysis is becoming a required addition to many design flows.

• Substrate coupling. This occurs in many types of circuits, from small radio-frequency (RF) designs to large embedded memories. The key aspect of the problem is the flow of ac currents in the substrate, generated by fast-switching (typically) digital devices. Designs where problems most often occur include embedded data converters or memories in large ASIC or ASSP ICs.

• Interconnect inductance modeling. This is an important issue for critical high-speed nets in both analog and digital IP design, as well as for chip-level interconnects. It is achieved through enhancements to the RLC interconnect extraction engines or through transmission-line models. Extraction techniques allow for higher capacity, but do not provide the high accuracy of transmission-line modeling.

With the large silicon area seen in SoC devices, other issues, such as electromagnetic coupling, also may exist. But for the most part, the four areas listed are the main issues SoC designers should worry about.

The solution to ensure minimal design risk involves a successful combination of robust CAD design flows; accurate analog-enabled CM OS technology processes and process design kit (PDK) enablement; and comprehensive, pragmatic (yet accurate) IP authoring and integration guidelines.

Robust CAD flows

Software design tools comprise a large part of a design team's budget and are critical to the success or failure of the project. The EDA industry is working hard to solve the major problems IC and pc-board designers face, and the subject of gigahertz-level SoCs is clearly a high-priority item. Technologies such as physically aware synthesis tools and nonlinear analog behavioral-modeling languages are important aids to design success. It is important that CAD engineers, supporting SoC design teams, are knowledgeable and experienced with the different EDA technologies needed. The evil of overengineering the CAD flow is equally important to avoid, and is in fact one of the biggest concerns for design teams — for example, do I really need this tool or is it an empty box?

Just as crucial as the CAD flow is the availability of accurate analog-enabled process technologies and PDKs, in the gigahertz-and-over frequency range. It is safe to assume that everything is converging on being analog in nature, but this assumption is more important in some designs than in others. For example, the performance of high-frequency FET devices is sensitive to many factors in their layout, including the location of the nearest substrate contact. In some circumstances, the unpredictability of these factors will lead to a very significant change in device performance in the built IC.

To avoid this, designers can use RF FETs, in this example, which have constrained layout topologies but highly predictable performance. The closure on this example is that the PDK must provide these PCells. Thus, both the process technology and the PDK have to be analog-enabled.

Comprehensive and pragmatic IP authoring and integration guidelines are another urgent requirement for gigahertz designs. The IP author now has added responsibilities of testing the core to work under conditions of higher levels of noise (many times of unknown magnitude, frequency and phase). This is a very difficult topic to solve, since there is no real commercial industry ready to profit from it. It is not specifically an EDA issue, nor is it the responsibility of an SoC integrator, and IP authors are not typically experienced enough outside their core design to know all the issues the integrator faces.

The Virtual Socket Interface Alliance (http://vsi.org) has a strategic mission to enable successful SoC design and IP import. VSIA's Signal Integrity specification document, together with the Analog Mixed-Signal and Implementation-Verification documents, provides a comprehensive set of guidelines for the author, when preparing IP for integration into gigahertz-level SoC devices.