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Industry Articles
Designing a next-generation video interface with thunderbolt technology
(Monday, August 19, 2013)
Optimized Memory Accessing Through Coupling of Byte Enable Signals
(Monday, August 19, 2013)
Extreme Programming
(Monday, August 19, 2013)
Deriving design margins for successful timing closure
(Thursday, August 15, 2013)
NVM memory: A Critical Design Consideration for IoT Applications
(Wednesday, August 14, 2013)
Free the Gadgets "Wireless Charging"
(Tuesday, August 13, 2013)
Is a single-chip SOC processor right for your embedded project?
(Tuesday, August 13, 2013)
Design planning for large SoC implemention at 40nm - Part 3
(Monday, August 12, 2013)
Supporting hardware assisted verification with synthesizable assertions
(Monday, August 5, 2013)
Critical Building Blocks of Smart Meters
(Monday, August 5, 2013)
Semiconductor industry strengths and weaknesses in the Asia Pacific region
(Tuesday, July 30, 2013)
Design and Implementation of SD Host Controller IP Core
(Tuesday, July 30, 2013)
A Novel Approach for improving OCV impact earlier in the design cycle
(Monday, July 29, 2013)
Powering SoCs: Where Do the Regulators Go?
(Monday, July 29, 2013)
Analyze high-speed interconnects
(Tuesday, July 23, 2013)
Navigating successful USB 3.0 compliance
(Tuesday, July 16, 2013)
Are we too Hard for Agile?
(Monday, July 15, 2013)
Clock Gate Logic Aware Design Closure
(Monday, July 15, 2013)
Design planning for large SoC implementation at 40nm - Part 2
(Monday, July 15, 2013)
Silicon Intellectual Property - Delivering value to customers
(Monday, July 8, 2013)
Basics of hardware/firmware interface codesign
(Monday, July 8, 2013)
Simulation - better than the real thing?
(Monday, July 8, 2013)
System Design in the Real World
(Thursday, July 4, 2013)
Design IP Faster: Introducing the C~ High-Level Language
(Monday, July 1, 2013)
Understanding in-loop filtering in the HEVC video standard
(Tuesday, June 25, 2013)
Link synchronization and alignment in JESD204B: Understanding control characters
(Monday, June 24, 2013)
ISS and architectural exploration
(Monday, June 24, 2013)
Latch-up Improvement For Tap Less Library Through Modified Decoupling Capacitors Cells
(Monday, June 24, 2013)
The Fundamentals of a SHA-256 Master/Slave Authentication System
(Thursday, June 20, 2013)
DDR3: A comparative study
(Thursday, June 20, 2013)
Functional Safety Certification for Subsystem Developers
(Monday, June 17, 2013)
Low Power Design for Testability
(Monday, June 17, 2013)
Creating highly reliable FPGA designs
(Friday, June 14, 2013)
Scaling NAND flash to 20-nm node and beyond
(Tuesday, June 11, 2013)
Using non-volatile memory IP in system on chip designs
(Tuesday, June 11, 2013)
A novel approach to ensure complete coverage for validation of communication protocols by inducing jitter and glitches in clock and data
(Monday, June 10, 2013)
Managing Requirements Tracking, Implementation and Sign-off for Embedded Systems
(Friday, June 7, 2013)
From Glue Logic to Subsystem: Altera's Second Decade
(Friday, June 7, 2013)
DO-254 Requirements Traceability
(Friday, June 7, 2013)
A need for static and dynamic Low Power Verification
(Monday, June 3, 2013)
Debugging FPGA-based video systems: Part 2
(Monday, June 3, 2013)
Soft memories in PD flow : Myth and Reality
(Tuesday, May 28, 2013)
Debugging FPGA-based video systems: Part 1
(Tuesday, May 28, 2013)
How to use ECC to protect embedded memories
(Monday, May 27, 2013)
DRC debugging challenges in AMS/custom designs at 20 nm
(Friday, May 24, 2013)
Address jitter and noise more effectively with DDR4, part1
(Wednesday, May 22, 2013)
Using a PCIe over Cabling-based platform to create hybrid FPGA/virtual platform prototypes
(Wednesday, May 22, 2013)
Generic DDR Behavioural Model
(Monday, May 20, 2013)
Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success
(Monday, May 20, 2013)
All eyes on Zynq SoC for smarter vision
(Friday, May 17, 2013)
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