Industry Expert Blogs
Have we reached the minimum size limits for analog IP?-November 23, 2009 |
In the last couple of postings I discussed technology scaling and it’s impact on analog IP. The point is that like digital gates, analog IP benefits from technology scaling but with a very different methodology – not using design tools but using different analog architectures: http://synopsysoc.org/theeyeshaveit/?p=242 illustrated USB 2.0 PHY scaling from 180 nm to 28 nm and http://synopsysoc.org/theeyeshaveit/?p=273 showed the example of a dual 10-bit, 80 MHz ADC in an 180 nm technology being five times smaller in 65 nm. So, if we go below 32/28 nm, will we continue to see this size reduction in analog IP?
Is there a size limit?