Industry Expert Blogs

For high speed memory interfaces, and for that matter any high speed interconnect such as source synchronous links or clock and data recovery SERDES – cost – coupled with power and speed have become the design targets. It is a bit like an optimization problem where the cost “variable” has a higher weighting. One of the main reasons is that these high performance interfaces initially designed for networking and high performance computer applications where cost had a lower weighting (over speed) now find their way into consumer devices.