Industry Expert Blogs
Making it Easy with Hard DDR PHY's-June 2, 2010 |
Our DDR team at Synopsys had a lot of fun creating a new video and ad campaign for our DDR PHYs. We call it the “HAAAAAARD PHY” campaign – check out the video at http://www.youtube.com/watch?v=7Ifj90O2N_M to see for yourself. Hopefully you’ll get some chuckles out of it too!
Synopsys DesignWare DDR PHYs are offered as “hard IP” meaning the PHY deliverables are primarily GDSII chip layout and the associated support material such as lef/lib/Verilog/LVS netlist, etc. This is in contrast to other DDR PHYs that are “soft IP” where the PHY is delivered as RTL and the customer must synthesize the “soft PHY”, possibly including other third party DLLs and/or PLLs and close timing. The timing closure problems with soft PHYs become more onerous as the frequency of the DDR interface increases.