Industry Expert Blogs

Every year there seem to be a few prevailing themes that emerge in chip design and EDA around the mid-summer /post-DAC timeframe. Usually they revolve around some high-level design tool concept such as electronic system-level (ESL) design, some aspect of SoC power optimization or design for manufacturing (DFM), or a wave of tools being introduced in some ‘new’ area. This year the chatter was the least tool-centric as I can remember in recent memory, which may not necessarily be a bad thing. In fact, it actually may be a sign of maturity that the EDA industry is focusing on the big picture challenges faced by IC and system designers.

In my mind, that biggest challenge is all about the tremendous shift toward true system-on-chip (SoC) design.