Industry Expert Blogs

As designers, we face many challenges during the SoC design cycle: the architecture goes through several iterations; bus speeds can vary; peripherals may be added or removed; the software becomes more complex. How can we ensure that our selection of memory will keep up with all these changes, some of which can occur a few weeks before functional closure?

We recently held a technical webinar at Synopsys to discuss how feature-rich, native SystemVerilog memory VIP can accelerate the verification of memory interfaces on most complex designs, focusing on 10 key areas where productivity is improved.