The big picture is that planar semiconductor transistors don't really work below 20nm. The reason is that the gate does a poor job of controlling the channel since too much channel is too far from the gate and so there is a lot of leakage even when the transistor is nominally off. So the channel needs to be made thinner. One way to do this is to make it into a thin fin and wrap the gate around it. That is what Intel, IBM and TSMC have all done and I reported on their papers at IEDM last month.

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