Design & Reuse

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Parameterized Interfaces and Reusable VIP (2 of 3)

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February 23, 2015

This is the second part of a three part series discussing SystemVerilog interfaces and strategies for dealing with parameterization.

In the first part of this series the basic concepts of SystemVerilog interfaces were introduced and the problems that parameterization of those interfaces introduce to testbench code was described. This post will describe a possible workaround for this problem, but one that comes with a price…

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