Are we there yet? All verification suffers from the problem of trying to decide when enough verification has been done. It is not possible to exhaustively simulate everything on a chip and so completeness cannot be the criterion (exhaustion, however, is optional, usually on the part of the design team).

At CDNLive in Bengaluru, Narender Kumar and Ravin Shah of ST Microelectronics (and Anshul Singhal of Cadence) presented on vManager Metric-Driven Signoff Platform for SoC Verification.

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