In the current semiconductor landscape, headlines are dominated by core counts, TOPS (Trillions of Operations Per Second), and very large bandwidths. However, hidden beneath the logic gates and HBM stacks lies a fundamental component that dictates the stability of the entire system: the Phase-Locked Loop (PLL).
As we transition into the era of PCIe Gen 6, 112G SerDes, and multi-die chiplet architectures, the margin for error in timing has all but vanished. The "Unit Interval" (UI)—the very small window of time available to transmit or receive a bit of data—is shrinking to picosecond levels. In this environment, the clock source is no longer just a heartbeat; it is the structural foundation of signal integrity.
At Key ASIC, our engineering teams are observing a critical inflection point. The traditional clocking architectures that served the industry well for the past decade are hitting a physical wall. To support the data rates of 64Gbps and beyond, we believe a fundamental architectural shift is necessary.
This article outlines our R&D team's upcoming PLL suitable for high-speed SerDes having ultra low jitter with LC- tank VCO, and supporting up to 16 GHz output clock to sample the data.
The Problem: When Physics Fights Back
For years, Ring Oscillator (RO) based PLLs were a good choice for a long bandwidth PLL with area budget but not good for very precise jitter. They are compact, scalable across process nodes, and offer wide tuning ranges. However, as frequency demands push past 10 GHz, the physics of Ring Oscillators becomes a liability.
Ring Oscillators rely on the delay of cascaded inverters. At high frequencies, maintaining a clean spectral output becomes exponentially difficult due to their inherent low quality factor (Q-factor). They are susceptible to thermal noise and, more critically, power supply noise. In a noisy, high-current and supply ripples RO translate into more phase noise (Jitter) to its output clock and make the eye worse in data-rate sampling of the high-speed SerDes.
When targeting next-generation applications requiring <800 femtoseconds (fs) of RMS jitter, the Ring Oscillator simply runs out of headroom. To break this barrier, we must move from a structure that is "flexible" to one that is "resonant."
The Solution: Returning to First Principles with LC-Tank Topologies
Key ASIC’s next-generation IP roadmap is centered around the low jitter PLL for high-speed SerDes to move over it we are using LC-Core to oscillate over 2GHz output clock of the Jitter. (LC-VCOs).
Unlike the noisy delay chain of a Ring Oscillator, an LC-tank utilizes an on-chip inductor (L) and a capacitor (C) to create a resonant circuit. This structure provides a significantly higher Q-factor. Imagine the difference between a rubber band (Ring Osc) and a tuning fork (LC-Tank). The tuning fork resists external disturbances and vibrates at a pure, singular tone.
Our ongoing architectural simulations target a jitter budget where the LC-VCO contribution is suppressed to under 400 fs. This establishes a "noise floor" that is physically impossible to achieve with traditional RO designs at equivalent power levels in this frequency band.
However, implementing LC-tanks in modern CMOS processes is not without challenges. Inductors consume silicon area, and their tuning range is narrower. Our R&D focus is currently solving the "tuning range vs. phase noise" trade-off, developing switched-capacitor banks and output divider that allow the PLL to cover the broad 2–16 GHz spectrum without sacrificing the purity of the resonance.
The Dual-Path Charge Pump Concept
While the LC-VCO sets the noise floor, the Charge Pump (CP) often introduces the "spikes" seen in a spectrum analyzer. In high-speed PLLs, current mismatch between the "UP" and "DOWN" currents in the charge pump creates reference spurs. These spurs are disastrous for ADC/DAC clocking and high-speed SerDes, as they manifest as deterministic jitter (DJ).
Key ASIC is currently developing a novel Dual-Path Charge Pump architecture to address this.
Standard designs often struggle to maintain current matching across Process, Voltage, and Temperature (PVT) variations. Our developing architecture introduces a "Replica Path" concept. While the primary path drives the loop filter for frequency acquisition, the secondary path works to maintain continuous charge balance.
The design target is reducing the mismatch between the UP and DOWN currents and resulting in minimize the spurs. So, the contribution in to the noise of the VCO is reduced which makes the PLL more suitable for our targeted specifications. Furthermore, we are using the Charge Pump with a wide programmable current range (targeting 20µA to 320µA) by using multiple stages with control circuitry. This programmability is crucial for SoC architects, allowing them to dynamically adjust the loop bandwidth—optimizing for fast locking during wake-up sequences or maximum jitter rejection during steady-state data transmission.
Noise Immunity
A PLL does not exist in a vacuum. It lives on a silicon die surrounded by billions of noisy, switching and current carrying transistors. A lab-perfect PLL can fail miserably in a real chip if it lacks immunity to Power Supply Noise (PSN).
Our design philosophy for this new IP places heavy emphasis on Power Supply Rejection Ratio (PSRR). We are simulating the architecture against aggressive noise profiles typical of high-performance computing environments.
The architectural goal includes:
- Deep-Submicron Regulators: Integrated LDOs specifically tuned to filter out switching noise frequencies.
- Optimized Loop Filters: Designing the multiple order passive loop filter to provide >80 dB of attenuation at critical offset frequencies (e.g., 1 MHz), creating a "spectral quiet zone" where it matters most.
Target Specifications & Application Relevance
While this IP is currently in the active development phase, our design targets are set to meet the rigorous demands of the next 5 years of computing:
- Output Frequency Range: 2 GHz to 16 GHz (Continuous coverage via capacitor banking and output Divider)
- Jitter Target: < 500 fs RMS (Integrated from 10kHz to 100MHz)
- Locking Time Target: < 100 µs (To support aggressive power-gating strategies)
These specifications are not random; they are derived from the requirements of 32G/56G SerDes, Precision ADC clocking, and AI Die-to-Die interconnects. By targeting these specs, we aim to provide a clocking foundation that allows our partners to utilize the full bandwidth of their interfaces without being bottlenecked by timing uncertainty.
Collaborating on the Future
Key ASIC believes that the best IP is built in collaboration with the architects who will use it.
As we move from architectural exploration to circuit design and eventual silicon validation, we are opening conversations with lead partners. We invite system architects and SoC leads to discuss their specific clocking challenges with us.
- Are you struggling with Ring Oscillator noise in your current designs?
- Does your roadmap call for tighter jitter budgets that your current IP library cannot support?
By sharing your requirements early, you can help influence the final characterization and feature set of this cutting-edge PLL.
The move to Low jitter PLL architectures at 16GHz is not just an upgrade; it is a necessity for the high-speed data era. Key ASIC is committed to solving the hard physical problems of timing, ensuring that when your next-generation chip comes back from the fab, the heartbeat of your system is strong, stable, and ready for mass production.
About Key ASIC
Key ASIC, listed on Bursa Malaysia (0143), is one of the world's leading turnkey ASIC design service companies, offering comprehensive support from design to chip production.
- Over 100 ASIC designs in mass production
- 100% successful ASIC tape out
- Over 150 silicon-proven IPs (e.g., DDR, SerDes, PCIe, USB, Ethernet, etc.)
As a foundry-independent company, we collaborate with top-tier foundries worldwide, providing unparalleled flexibility and expertise to meet our customers' diverse needs.
Key ASIC is here to provide the best partnership for your ASIC business.
Please feel free to contact us via email: info@keyasic.com
Note: The technical specifications mentioned in this article represent current R&D design targets and are subject to change based on final silicon characterization.