Design & Reuse
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34 IP
1
10.0
Reed Solomon Forward Error Correction Encoder Decoder
The Reed Solomon Forward Error Correction (RS FEC) IP is a highly optimized and silicon agnostic implementation of the RS FEC encoder and decoder algo...
2
10.0
Library of mathematical and floating point (FP) components
Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating point (FP) components th...
3
6.0
Single- and double-precision IEEE-754 floating-point unit
The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu...
4
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
5
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
6
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
7
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
8
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
9
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
10
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
11
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
12
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
13
3.0
Color Camera Sensor Bayer Decoder
Today most common single-chip cameras use CMOS sensors with pixels arranged in Bayer color pattern. Bayer filter in front of the sensor embeds color i...
14
2.0
4-Quadrant Arctan Function
Function φ = atan2(y,x) calculates the 4-quadrant inverse tangent in the range -Pi to Pi. Functionally equivalent to the atan2 function in 'C' an...
15
2.0
Pipelined Divider
Function y = a / b is a very high-speed divider with configurable dividend and divisor width. Inputs and outputs may be specified as either signed or...
16
2.0
Pipelined Multiplier
Function y = a * b is a high-speed multiplier with configurable width and depth. Inputs and outputs may be specified as either signed or unsigned val...
17
2.0
Pipelined Square Root
Function y = √x is a fully scalable square-root function with configurable data width. Inputs and outputs are unsigned integers. An n-bit inpu...
18
2.0
Floating-point Adder
High-speed fully pipelined 32-bit floating-point adder/subtracter based on the IEEE 754 standard. Results have a latency of 5 clock cycles. Ideal for...
19
2.0
Floating-point Divider
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard. Features a generic latency from 2 to 49 clock cycles. Ideal ...
20
2.0
Floating-point Multiplier
High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard. Results have a latency of only 4 clock cycles. Ideal for ...
21
2.0
Floating-point Square-root
High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cy...
22
2.0
Floating-point to Fixed-point Converter
Converts 32-bit floating-point numbers to fixed-point representation. The fixed-point output has a configurable word and fraction width. Floating-poin...
23
2.0
Cosine Function
Function y = cos(x) calculates the cosine of an angle in radians. It has a high-speed, fully pipelined architecture and uses a polynomial with dynamic...
24
2.0
Arctan Function
Function y = atan(x) calculates the inverse tangent of a fraction. It has a high-speed, fully pipelined architecture and uses a polynomial with dynam...
25
1.0
SinCos Function
Function calculates the Sine and Cosine of input x in radians. Inputs are 18-bit signed values in the range -Pi to Pi. Output values are 17-bit sign...
26
1.0
Sine Function
Function y = sin(x) calculates the sine of an angle in radians. It has a high-speed, fully pipelined architecture and uses a polynomial with dynamic c...
27
0.0
Floating point adder
Floating point adder...
28
0.0
Floating point MAC
Floating point MAC...
29
0.0
Floating point multiplier
Floating point multiplier...
30
0.0
DolphinWare Arithmetic Components Ips
Dolphin Technology provides DolphinWare Arithmetic Components IPs, consist of Math Operators and Converters....
31
0.0
DolphinWare Control Logic Ips
Dolphin Technology provides DolphinWare Control Logic IPs, consist of Arbiter and FIFO....
32
0.0
DolphinWare Data Integrity Ips
Dolphin Technology provides DolphinWare Data Integrity IPs, consist of Encoders, Decoders and Error Correction....
33
0.0
DolphinWare Logic Components Ips
Dolphin Technology provides DolphinWare Logic Components IPs, consist of Counters, Registers and MUXs....
34
0.0
DolphinWare Verification Ips
Dolphin Technology provides DolphinWare Verification IPs (VIPs), consist of AXI4, APB, SD4.0/UHS-II, I2C, I3C, I2S....