Design & Reuse
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137 IP
1
100.0
TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
Universal LVDS-based interfaces supporting variety of Tx and Rx configurations....
2
100.0
TSMC GF LVDS Tx/Rx with optional CMOS I/O
Flexible I/O cell for data and clock applications that supports differential (and optionally single-ended) Tx and Rx capabilities with no external com...
3
25.0
LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF. The differential voltage swing can be programmable from...
4
20.0
MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI ...
5
15.0
Library of LVDS IOs cells for TSMC 40LP
The nSIO2000_TS40LP_2V5_1V1 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.1V or 1.8V/1.1V, designed ...
6
15.0
Library of LVDS IOs cells for TSMC 65LP
The nSIO2000_TS65LP_2V5_1V2 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.2V or 1.8V/1.2V, designed ...
7
15.0
Four Channel (4CH) LVDS Receiver in TSMC 40LP
The MXL-LVDS-4CH-RX-T-40LP is a high-performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data ...
8
10.0
Differential Output Buffer - TSMC 6FF
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements ...
9
10.0
Differential Output Buffer - TSMC N5
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements ...
10
10.0
Differential Receiver - TSMC 7FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
11
10.0
Differential Signal Receiver - TSMC 6FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
12
10.0
Differential Signal Receiver - TSMC N5
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
13
8.0
IGALVDT08B, TSMC CLN28HPM LVDS TX/RX Combo IO
The IGALVDT08B contain a differential driver (TX) and a re-ceiver (RX) for LVDS interface. It supports the data rate up to 1.5Gbps. There are four mac...
14
8.0
IGALVDV05A, TSMC CLN12FFC 6-Channel LVDS Transmitter PHY
IGALVDV05A is a 6-channel LVDS Transmitter PHY IP, which is used mainly in Flat-panel Display. It enables larger, higher resolution displays and lower...
15
6.0
LVDS 10 bits dual port transmitter
...
16
5.0
2.8 Gbps LVDS IO
The LVDS I/O is a single macro (input, output and reference block). Both driver and receiver operating up to 1.4GHz (2.8 Gbps ). The Driver is designe...
17
5.0
Fully-integrated Low Voltage Differential Signaling (LDVS) transceiver
The LVDS Transceiver is a fully integrated Low-Voltage Differential Signaling (LVDS) Analog Front End (AFE) including one flow-through driver and two ...
18
3.0
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
Key attributes of our TSMC 65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a lo...
19
2.0
A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF
Key attributes of the GlobalFoundries 65nm IO library are dual selectable drive strengths and independent input & output enable / disable. The GPIO ce...
20
2.0
High-voltage solutions in baseline TSMC and GlobalFoundries technology
Certus is pleased to offer High-voltage ESD solutions across multiple baseline technologies. Distinguishing Certus is our ability to provide high-vol...
21
2.0
LVDS I/O Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rate...
22
2.0
LVDS I/O Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...
23
2.0
LVDS I/O Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...
24
2.0
LVDS I/O Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rate...
25
2.0
LVDS IO Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...
26
2.0
LVDS IO Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...
27
2.0
LVDS RX & TX IOs in multiple foundry technology
Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies. The Certus LVDS solutions are ANSI/TIA/EIA-644-A compliant a...
28
1.0
4 Gbps DDR CML receiver and transmitter
055TSMC_CML_01 is a library including: - CML receiver (CML_RX); - CML transmitter (CML_TX). The CML_RX block is intended to receive a CML signal a...
29
1.0
800MHz LVDS Cell Set for 180nm
The OT3910 is a set of cells for implementing 800Mb DDR (400MHz) LVDS IO in 180n CMOS processes. Includes transmitter and receiver IO's. Also core ...
30
1.0
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v SUBLVDSTX
...
31
1.0
GLOBALFOUNDRIES 28nm SLP sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
32
1.0
GLOBALFOUNDRIES 65nm LVDS Transmitter
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...
33
1.0
Sony Camera LVDS Interface
The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an ext...
34
1.0
GSMC 0.11um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
35
1.0
GSMC 0.18um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
36
1.0
LVDS
This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint. The LVDS TX & RX IP is specified for ope...
37
1.0
LVDS TX
...
38
0.3729
1.8V Secondary Oxide LVDS & LVPECL I/O Combo Pad - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF
Dolphin Technology's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR4/3/2, LPDDR3/2, DDR PHY, LVDS, LVPECL, I2...
39
0.3729
1.8V Secondary Oxide LVDS combo pad - TSMC 5nm 5FF
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
40
0.3729
1.8V Secondary Oxide LVDS pad - TSMC 22nm 22ULP,ULL
Dolphin Technology's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR4/3/2, LPDDR3/2, DDR PHY, LVDS, LVPECL, I2...
41
0.3729
1.8V Secondary Oxide LVDS pad - TSMC 28nm 28HP,HPL,LP,ULP,HPC,HPC+,HPM
Dolphin Technology's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR4/3/2, LPDDR3/2, DDR PHY, LVDS, LVPECL, I2...
42
0.3729
1.8V Secondary Oxide LVDS pad - TSMC 6nm 6FF
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
43
0.118
8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process
8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process...
44
0.118
0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
45
0.118
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces...
46
0.118
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process...
47
0.118
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process...
48
0.118
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process...
49
0.118
3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process...
50
0.118
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process...