Company
design-reuse.com
D&R China
Blogs
Industry Articles
D&R Events
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC Days 2021
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
IP-SoC 2021
Subscribe to D&R SoC News Alert
English
Mandarin
Register
Login
Menu
Home
Search IP Core
News
Blogs
Articles
D&R Events
Subscribe to D&R SoC News Alert
Register
Login
News
Center
Foundation IP
Analog IP
Interface IP
Interconnect IP
Memory Controller
Peripheral Controller
Wireless IP
Wireline IP
Processor IP
RISC-V
AI Core
Automotive IP
Security IP
IoT
Media IP
Avionics / Space IP
Verification IP
Verification Platform
Asic & IP Design Center
IP-SoC Days
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC Days 2021
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
IP-SoC 2021
Browse Foundation
Arithmetic & Mathematic (34)
Embedded Memories (1008)
I/O Library (952)
Standard cell (745)
CAM (27)
Diffusion ROM (3)
DRAM (2)
Dual-Port SRAM (22)
EEPROM (30)
Flash Memory (36)
FTP (9)
Metal ROM (1)
MTP (39)
OTP (161)
RAM (286)
Register File (249)
ROM (89)
RRAM (1)
Single-Port SRAM (21)
Via ROM (12)
Other (20)
ESD Protection (69)
General-Purpose I/O (GPIO) (412)
High-speed (137)
LVDS (39)
Memory Interfaces (14)
Special (281)
You must be registered with the D&R website to view the full search results, including:
Complete datasheets for
IP Core
products
Contact information for
IP Core
suppliers
Please
log in
here to your account.
New user ?
Signup here
.
39 IP
1
15.0
MIPI D-PHY CSI-2 TX (Transmitter) in TowerJazz 65BSB
The MXL-LVDS-0p6G-DPHY-1p2G-CSI-2-TX-TW-065BSB is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Allian...
2
15.0
Four Channel (4CH) LVDS in TSMC 40LP
The MXL-LVDS-4CH-TX-T-40LP is a high-performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock f...
3
10.0
High speed universal LVDS Transceiver
Silvaco’s Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. ...
4
6.0
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
...
5
3.0
A 2Gbps LVDS Tranceiver in TSMC 28nm
This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity. Eng...
6
3.0
A TSMC 16nm 2Gbps LVDS/SLVS Combo Transceiver
This combo transceiver is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die ...
7
3.0
1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in TSMC 65nm
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain cells, 3.3V & 5V analog cells, OTP program c...
8
3.0
HDMI, LVDS, RF and Analog Pads Library in 45nm / 40nm
A 1.0V to 5V Analog IO Library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in 45nm/40nm HPM processes. This library is a col...
9
2.0
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver
Certus Semiconductor’s 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-inten...
10
2.0
High-Speed LVDS (SERDES) Transceiver
High-speed LVDS (SERDES) transceiver with up to 8 serial data lanes, generic data width and integrated asynchronous FIFO. Ideal for standard LVDS link...
11
2.0
LVDS IO Pad Set
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates ...
12
1.0
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias. The LVDS transmitter consists of a current source (nominal 3.5mA) tha...
13
1.0
GLOBALFOUNDARIES 22nm FDSOI LVDS Transceiver Pad
The LVDS IO library provides IO cells for LVDS transmitter and receiver. The transmitter (TX) supports LVDS differential driver mode, and the receiver...
14
1.0
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The L...
15
1.0
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can support transmission ...
16
1.0
Programmable Special IO in SMIC0.13um
AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extreme...
17
0.3729
2.5V Secondary Oxide LVDS pad - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
18
0.3729
1.8V Secondary Oxide LVDS combo pad - TSMC 3nm
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
19
0.3729
1.8V Secondary Oxide LVDS combo pad - TSMC 4nm 4FF/4P
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
20
0.118
LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process
2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process....
21
0.118
LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process
DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process....
22
0.118
LVDS Receiver IP, 700Mbps, UMC 0.13um SP/FSG process
Low Power LVDS Receiver 700Mbps, UMC 90nm SP/RVT Low-K Logic process....
23
0.118
LVDS Receiver IP, UMC 90nm SP process
DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process....
24
0.118
LVDS Rx IO IP, 500Mbps, UMC 90nm LL process
Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process....
25
0.118
LVDS Rx IO IP, UMC 0.18um G2 process
0.13um LVDS RX IO PAD, UMC 0.13um HS/HVT-FSG process....
26
0.118
LVDS Rx IO IP, UMC 0.18um Logic process
LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process....
27
0.118
LVDS Rx IO IP, UMC 90nm SP process
0.18UM RX (PAD), UMC 0.18um GII Logic process....
28
0.118
LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process
2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process....
29
0.118
LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process
2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process....
30
0.118
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process
2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process....
31
0.118
LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process
8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process....
32
0.118
LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process
2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process....
33
0.118
LVDS Transmitter IP, Tx IO, UMC 55nm SP process
0.18um TX PAD, UMC 0.18um Logic RVT-FSG process....
34
0.118
LVDS Tx IO IP, UMC 90nm SP process
LVDS TX Pad, UMC 0.35um Logic process....
35
0.0
1.25 Gbps LVDS IPs library
028TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reduced range link receive...
36
0.0
1.25 Gbps LVDS IPs library
040TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Reference current/voltage so...
37
0.0
666 Mbps LVDS Transceiver IP
The MXL-TXRX-LVDS is a LVDS transceiver implemented in digital CMOS technology. It supports up to 666 Mbps. It is compatible with IEEE Std 1596, EIA-6...
38
0.0
MIPI D-PHY/LVDS Combo DSI RX (Receiver) in TSMC 110G
The MXL-DPHY-LVDS-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard...
39
0.0
Up to 400 Mbps DDR LVDS receiver
130GF_LVDS_01 is a LVDS receiver with data rate up to 400 Mbps (DDR mode). The LVDS receiver converts input LVDS signal to differential CMOS 1.5V stan...