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2786 IP
651
1.0
SMIC 0.15um SSTL2
VeriSilicon SMIC 0.15um 1.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
652
1.0
SMIC 0.15um SSTL3
VeriSilicon SMIC 0.15um 1.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
653
1.0
SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.15um LV High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.15um Lo...
654
1.0
SMIC 0.16um 1.8V<->3.3V level shifter,1.8v/3.3v operating voltage
SMIC 0.16um 1.8V3.3V Level Shfiter Library...
655
1.0
SMIC 0.16um 3.3V Standard Cell Library,1.8v operating voltage
SMIC 0.16um 3.3V Standard Cell Library...
656
1.0
SMIC 0.16um 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.16um 9T High-Density Standard Cell Library...
657
1.0
SMIC 0.16um IO Library
SMIC 0.16um process 1.8v/3.3v Generic IO library...
658
1.0
SMIC 0.16um Isolation Cell Library,1.8v operating voltage
SMIC 0.16um Isolation Cell Library...
659
1.0
SMIC 0.16um LL IO Library
SMIC 0.16um LL process 1.8v/3.3v Generic IO library...
660
1.0
SMIC 0.16um Low Leakage 7 track High Density Standard Cell Library,1.8v operating voltage
SMIC 0.16um Low Leakage 7T High-Density Standard Cell Library...
661
1.0
SMIC 0.16um Low Leakage 9T Standard Cell Library
SMIC 0.16um Low Leakage 7T High-Density Standard Cell Library...
662
1.0
SMIC 0.18um 1.8V/3.3V Clockgating Cell Library
VeriSilicon SMIC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Co...
663
1.0
SMIC 0.18um 1.8V/3.3V DUP I/O Library
VeriSilicon SMIC 0.18um 1.8V/3.3V DUP I/O Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMI...
664
1.0
SMIC 0.18um 1.8V<->3.3V level shifter,1.8v/3.3vv operating voltage
SMIC 0.18um 1.8V3.3V Level Shfiter Library...
665
1.0
SMIC 0.18um 3.3V Standard Cell Library,3.3v operating voltage
SMIC 0.18um 3.3V Standard Cell Library...
666
1.0
SMIC 0.18um 3.3V Standard Cell Library,3.3v operating voltage
SMIC 0.18um 3.3V Standard Cell Library...
667
1.0
SMIC 0.18um 7 track High Density Standard Cell Library,1.8v operating voltage
SMIC 0.18um 7T High-Density Standard Cell Library...
668
1.0
SMIC 0.18um 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.18um 9T High-Density Standard Cell Library...
669
1.0
SMIC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.16um Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.16um Logic 1P6M Salic...
670
1.0
SMIC 0.18um Crystal Oscillator IO_01
This crystal oscillator IO pad is designed for 1.8V OSC power supply. The IO gives clock signal under 1.8V power supply. The Pierce oscillator works i...
671
1.0
SMIC 0.18um High Density Standard Cell Library
...
672
1.0
SMIC 0.18um IO Library
SMIC 0.18um process 1.8v/3.3v Generic IO library...
673
1.0
SMIC 0.18um IO Library
...
674
1.0
SMIC 0.18um Isolation Cell Library,1.8v operating voltage
SMIC 0.18um Isolation Cell Library...
675
1.0
SMIC 0.18um LL 5v IO Library
SMIC 0.18um LL process 1.8v/5v Generic IO library...
676
1.0
SMIC 0.18um LL IO Library
SMIC 0.18um LL process 1.8v/3.3v Generic IO library...
677
1.0
SMIC 0.18um Low Leakage 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.18um Low Leakage 9T High-Density Standard Cell Library...
678
1.0
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The L...
679
1.0
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can support transmission ...
680
1.0
SMIC 0.18um ROM Compiler
...
681
1.0
SMIC 0.18um Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.18um Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salic...
682
1.0
SMIC 0.18um Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler for Linux
VeriSilicon SMIC 0.18um Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salic...
683
1.0
SMIC 0.18um Single-Port/Two-Port Register File Compiler
...
684
1.0
SMIC 0.18um SSTL2
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
685
1.0
SMIC 0.18um SSTL3
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
686
1.0
SMIC 0.18um SSTL_18 I/O
SSTL_18 (Stub Series Terminated Logic for 1.8v) is an electrical interface commonly used with DDR2....
687
1.0
SMIC 0.18umLL 90% shrunk Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.16um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.1...
688
1.0
SMIC 0.18umLL Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.1...
689
1.0
SMIC 0.18umLL Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler for Linux
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.1...
690
1.0
SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
691
1.0
SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library
VeriSilicon SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
692
1.0
SMIC 0.25um High Density Standard Cell Library
...
693
1.0
SMIC 0.25um ROM Compiler
...
694
1.0
SMIC 0.25um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon SMIC 0.25um High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.25um Logic...
695
1.0
SMIC 0.25um Single-Port/Two-Port Register File Compiler
...
696
1.0
SMIC 55nm LP Multiple Power Supply IO library
Multiple power supply IO library for SMIC55nm low power 1.2v/2.5v process...
697
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
698
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
699
1.0
SMIC 90nm 9T Standard Cell Library - HVT, 1.2v operating voltage
SMIC 90nm Low-Leakage 9T Standard Cell Library...
700
1.0
SMIC 90nm 9T Standard Cell Library - RVT, 1.2v operating voltage
SMIC 90nm Low-Leakage 9T Standard Cell Library...
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