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2786 IP
751
1.0
GSMC 0.18um 1.8V/3.3V Clockgating Cell Library
VeriSilicon GSMC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporatio...
752
1.0
GSMC 0.18um 1.8V/3.3V DUP I/O Library
VeriSilicon GSMC 0.18um 1.8V/3.3V DUP I/O Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18u...
753
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (02) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing (GSMC) 0....
754
1.0
GSMC 0.18um 1.8V/3.3V Multiple I/O
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (03) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporati...
755
1.0
GSMC 0.18um 1.8V<->3.3V Level Shifter Library, 1.8v/3.3v operating voltage
GSMC 0.18um 1.8V3.3V Level Shfiter Library...
756
1.0
GSMC 0.18um 3.3V Standard Cell Library, 3.3v operating voltage
GSMC 0.18um 3.3V Standard Cell Library...
757
1.0
GSMC 0.18um 3.3V Standard Cell Library, 3.3v operating voltage
GSMC 0.18um 3.3V Standard Cell Library...
758
1.0
GSMC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon GSMC 0.16um High-Speed Synchronous Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.16um Logic/Analog ...
759
1.0
CSMC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
VeriSilicon CSMC 0.16um High-Speed Synchronous Memory Compiler optimized for CSMC TECHNOLOGIES CORPORATION Fab2 0.16um MS/RF process can flexibly gene...
760
1.0
GSMC 0.18um 9track Standard Cell Library, 1.8v operating voltage
GSMC 0.18um 9 track Standard Cell Library...
761
1.0
GSMC 0.18um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between them can be up to 650Mhz. The LVDS...
762
1.0
CSMC 0.18um Clock Gating Cell Library, 1.8v operating voltage
CSMC 0.18um Clock Gating Cell...
763
1.0
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/3.3v Generic IO library...
764
1.0
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/5v Generic IO library...
765
1.0
GSMC 0.18um Crystal Oscillator IO
This is a crystal oscillator IO pad designed for low-power consumption application. The OSC power supply is 3.3V, and the IO pad provides clock signal...
766
1.0
GSMC 0.18um IO Library
GSMC 0.18um process 1.8v/3.3v Generic IO library...
767
1.0
CSMC 0.18um IO Library
CSMC 0.18um process 1.8v/3.3v Generic IO library...
768
1.0
GSMC 0.18um Low Power 9track Standard Cell Library, 1.8v operating voltage
GSMC 0.18um Low Power 9 track Standard Cell Library...
769
1.0
GSMC 0.18um LP IO Library
GSMC 0.18um LP process 1.8v/3.3v Generic IO library...
770
1.0
GSMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon GSMC 0.18um High-Speed Synchronous Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/Analog ...
771
1.0
CSMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
VeriSilicon CSMC 0.18um High-Speed Synchronous Memory Compiler optimized for CSMC TECHNOLOGIES CORPORATION Fab2 0.18um MS/RF process can flexibly gene...
772
1.0
CSMC 0.18um Standard Cell Library, 1.8v operating voltage
CSMC 0.18um Standard Cell Library...
773
1.0
GSMC 0.18um ULL IO Library
GSMC 0.18um ULL process 1.8v/3.3v Generic IO library...
774
1.0
GSMC 0.18um Ultra Low Leakage 9track Standard Cell Library, 1.8v operating voltage
GSMC 0.18um Ultra Low Leakage 9 track Standard Cell Library...
775
1.0
GSMC 0.18umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon GSMC 0.18um High-Speed Synchronous IBLP Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P...
776
1.0
GSMC 0.18umOTP Single-Port/Dual-Port SRAM and Diffusion ROM Compiler
VeriSilicon GSMC 0.18um G9 3.3V Synchronous Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Generic 1P3M 3.3...
777
1.0
GSMC 0.18umULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon GSMC 0.18um Ultra Low Leakage Process High-Speed Synchronous Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (...
778
1.0
GSMC 0.25um Standard Cell Library, 2.5v operating voltage
GSMC 0.25um Standard Cell Library...
779
1.0
GSMC 0.25um IO Library
GSMC 0.25um process 2.5v/3.3v Generic IO library...
780
1.0
GSMC 0.25um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon GSMC 0.25um High-Speed Synchronous Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.25um Logic 1P5M Sa...
781
1.0
TSMC 12nm FFC 6track Delay Cells
TSMC 12nm FFC 6 track High Density Delay Cells...
782
1.0
CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
VeriSilicon CSMC 0.13μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Central Semiconductor Manufacturing Corporation (CSMC...
783
1.0
GSMC16RF process VPPIO, provides 6.5V power supply IO pads for OTP application.
VeriSilicon GSMC 0.16um RF 1.8V/3.3V VPPIO_DUP_01 IO library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (...
784
1.0
ST28nm LVDS Transmitter
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...
785
1.0
Huali 28nm HKCP process Multiple Power Supply IO library
The Multiple I/O Library supports both 2.5V analog IO cells & 3.3V digital IO cells. Digital IO contains 5V tolerance, open-drain & OSC cells. This li...
786
1.0
LVDS
This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint. The LVDS TX & RX IP is specified for ope...
787
1.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
788
1.0
LVDS TX
...
789
1.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
790
1.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
791
0.3729
A memory BIST solution which has been optimized for Dolphin memories
Dolphin Technology now provides a memory BIST solution which has been optimized for Dolphin memories. It supports all Dolphin memory compilers, includ...
792
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, supports process G/LV
Memory Compilers...
793
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, supports process GC
Memory Compilers...
794
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF
Memory Compilers...
795
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF
Memory Compilers...
796
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF+GL/FF+LL/FFC
Memory Compilers...
797
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/FF+
Memory Compilers...
798
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/P
Memory Compilers...
799
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/P
Memory Compilers...
800
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FFC/FFC+
Memory Compilers...