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2786 IP
2351
0.118
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 7-Track POWERSLASH Cell Library....
2352
0.118
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....
2353
0.118
Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....
2354
0.118
Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track POWERSLASH standard Core Cell Library (C35)....
2355
0.118
Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....
2356
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track Standard POWERSLASH Core Cell Library (C35)....
2357
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed POWERSLASH Cell Library (C40)....
2358
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library....
2359
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....
2360
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30 RVT)....
2361
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LPLUS (C38)....
2362
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35)....
2363
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 7-Track POWERSLASH Cell Library....
2364
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....
2365
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library....
2366
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....
2367
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track POWERSLASH Cell Library (C35)....
2368
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....
2369
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells....
2370
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Powerlash Core Cell Library....
2371
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit....
2372
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library....
2373
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library....
2374
0.118
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process Low Power standard Cell Library....
2375
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process
UMC 0.11um LL/FSG Logic process high density POWERSLASH Core Cell Library....
2376
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process FSC0H_J POWERSLASHKit core Library....
2377
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library....
2378
0.118
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process
UMC 0.13um SP FSG Logic process high density POWERSLASH Core Cell Library....
2379
0.118
Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler....
2380
0.118
Dual Port SRAM Compiler IP, Output: 1.8432MHz, UMC 40nm LP process
UMC 40nm LP Logic process synchronous high density Dual Port SRAM memory compiler....
2381
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process
UMC 40nm Logic process synchronous high density Dual Port SRAM memory compiler with redundancy....
2382
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process
UMC 55nm eHV process, Dual Port SRAM compiler with row redundancy option....
2383
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Dual Port SRAM with redundancy feature....
2384
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler with redundancy....
2385
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm 1.0V Standard Performance (SP) Low-K Logic process synchronous, high density, Dual Port SRAM with row redundancy option....
2386
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process
UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler with redundancy elements and bist testing interfa...
2387
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm LL process
UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler wiht redundancy elements....
2388
0.118
Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process
UMC 65nm SP/RVT Logic and HVT Low-K process synchronous, high density, Dual Port SRAM compiler with the row redundancy option....
2389
0.118
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash HS process, Dual Port SRAM compiler....
2390
0.118
Dual Port SRAM Compiler IP, UMC 0.11um eFlash/LL process
UMC 0.11um eFlash LL process Dual Port SRAM compiler....
2391
0.118
Dual Port SRAM Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE Logic process synchronous High-density Dual Port SRAM memory compiler....
2392
0.118
Dual Port SRAM Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/RVT Logic process synchronous high density Dual Port SRAM memory compiler....
2393
0.118
Dual Port SRAM Compiler IP, UMC 0.11um LL process
UMC 0.11um low leakage Logic process synchronous high density Dual Port SRAM memory compiler....
2394
0.118
Dual Port SRAM Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Advanced Enhancement) Logic process synchronous high density Dual Port SRAM memory compiler....
2395
0.118
Dual Port SRAM Compiler IP, UMC 0.11um SP process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler....
2396
0.118
Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous high density Dual Port SRAM memory compiler with input wrapper Mux....
2397
0.118
Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Dual Port (2RW) SRAM memory compiler....
2398
0.118
Dual Port SRAM Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous high density Dual Port (2RW) SRAM memory compiler....
2399
0.118
Dual Port SRAM Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous high density Dual Port (2RW) SRAM memory compiler....
2400
0.118
Dual Port SRAM Compiler IP, UMC 0.153um MS process
UMC 153nm Mixed-Mode/Logic process synchronous high density Dual Port SRAM memory compiler....
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