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2786 IP
2501
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V +/-10% / 1.1 V +/- 10%)
TSMC 180 BCD, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phen...
2502
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
TSMC 180 G, SESAME HD DV optimized for high density and low power, with characterizations taking into account physical phenomena linked to low voltage...
2503
0.0
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME HD provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells....
2504
0.0
6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tr...
2505
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6 track High Density standard cell library at TSMC 180 nm
TSMC 180 uLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells and 1P3M ...
2506
0.0
6 track High Density standard cell library at TSMC 180nm
TSMC 180 RF, SESAME HD optimized for high density and low power, RF models...
2507
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLP, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tra...
2508
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-t...
2509
0.0
9 track Near Threshold Voltage standard cell library at TSMC 55 nm
TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing users to share the s...
2510
0.0
8 track thick oxide standard cell library at TSMC 130 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 130 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2511
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2512
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 RF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
2513
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 LPeF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through th...
2514
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 LP, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2515
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 uLL, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
2516
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi...
2517
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2518
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
2519
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2520
0.0
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2521
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest ...
2522
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 LPeF, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
2523
0.0
V-by-One Tx IP, Silicon Proven in SMIC 40LL
V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment. V-by-One® HS Standard de...
2524
0.0
3.125 Gbps DDR 1-channel CML transmitter
065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter...
2525
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3.125 Gbps DDR CML receiver
065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD...
2526
0.0
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins (en_rx, ten, t_cal ar...
2527
0.0
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
The MXL-LVDS-RX-4CH is a high performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are org...
2528
0.0
1.25 Gbps LVDS IPs library
028TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reduced range link receiver LVDS...
2529
0.0
1.25 Gbps LVDS IPs library
040TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Reference current/voltage source (...
2530
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spac...
2531
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
2532
0.0
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
2533
0.0
7.5 Gbps DDR CML IPs library
040TSMC_CML_01 is a library including: • CML receiver (CML_RX); • CML transmitter (CML_TX). • Reference current/voltage source (CML_RS); • Refe...
2534
0.0
2.5V 5V Tolerant GPIO Inline IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...
2535
0.0
2.5V 5V Tolerant GPIO Staggered IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...
2536
0.0
2.5V General Purpose Inline IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...
2537
0.0
2.5V General Purpose Staggered IO Pad Set
A full range of power pads is provided to enable the system designer different options for separate core power (VDD and VSS) and separate I/O padring ...
2538
0.0
1.8V Secondary Oxide LVDS pad - TSMC 7nm 7FF,FF+
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
2539
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I/O LIbrary
Specialty I/O solutions - Higher voltage tolerance - higher ESD robustness - Configurable...
2540
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200 Mbps LVDS IP library
055TSMC_LVDS_03 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reference current/voltage genera...
2541
0.0
500Mbps LVDS IP library
180TSMC_LVDS_10 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Transceiver LVDS driver (R...
2542
0.0
1024-bit EEPROM IP with configuration 32p2w16bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x 2(word per page) x 3...
2543
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2048bits EEPROM with configuration 16p8w16bit
130GF_EEPROM_05 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 2048bit, which is organized as 16 pages of 8...
2544
0.0
104x1 Bits OTP (One-Time Programmable) IP, VI- 0.15μm 1.8V/6V BCD G2 EPI Process
The ATO00104X1VI150BIO2N2B is organized as a 104-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μ...
2545
0.0
512-bit EEPROM with configuration 16p1w32bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits (32(bit per word) x 1(word per page) x 16...
2546
0.0
512bit EEPROM IP with configuration 16p2w16bit
180SMIC_EEPROM_09 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits which is organized as 16 pages of...
2547
0.0
512x1 Bits OTP (One-Time Programmable) IP, HHGrac- 95nm 1.5V/5V Embedded SONOS Flash (EF095LP)
The ATO00512X1HH095SON3NA is organized as a 512-bits by 1 one-time programmable in parallel mode. This is a kind of non-volatile memory fabricated in ...
2548
0.0
512x1 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V CMOS 18B Process
The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP). This is a type of non-volatile memory fabricated in MXI- 0.18μ...
2549
0.0
512x1 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V CMOS 18B Process,Using 5V devices only
The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in MXI- 0.18μm ...
2550
0.0
512x1 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V CMOS 18B1(BCD_EPI)
The ATO00512X1MX180B152NA is organized as a 512x1 one-time programmable(OTP). This is a type of non-volatile memory fabricated in MXI- 0.18μm CMOS 18B...