Design & Reuse
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2776 IP
2701
0.0
LogicFlash® Embedded MTP in UMC 180nm~110nm
LogicFlash® MTP是一种基于CMOS工艺的嵌入式非挥发性存储器技术，基于逻辑工艺实现，无需增加额外光罩层次，或通过增加1层额外光罩，缩减IP面积，适合于1KB~64KB的中等容量应用，同时提供高达2万次的擦写次数。 LogicFlash®技术可以在0.18um到55nm的Logic/BC...
2702
0.0
DolphinWare Arithmetic Components Ips
Dolphin Technology provides DolphinWare Arithmetic Components IPs, consist of Math Operators and Converters....
2703
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DolphinWare Control Logic Ips
Dolphin Technology provides DolphinWare Control Logic IPs, consist of Arbiter and FIFO....
2704
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DolphinWare Data Integrity Ips
Dolphin Technology provides DolphinWare Data Integrity IPs, consist of Encoders, Decoders and Error Correction....
2705
0.0
DolphinWare Logic Components Ips
Dolphin Technology provides DolphinWare Logic Components IPs, consist of Counters, Registers and MUXs....
2706
0.0
DolphinWare Verification Ips
Dolphin Technology provides DolphinWare Verification IPs (VIPs), consist of AXI4, APB, SD4.0/UHS-II, I2C, I3C, I2S....
2707
0.0
Foundry sponsored - Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
Foundry sponsored - Single port SRAM compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range up to...
2708
0.0
Four Channel (4CH) LVDS Receiver in TSMC 40LP
The MXL-LVDS-4CH-RX-T-40LP is a high-performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data ...
2709
0.0
Four Channel (4CH) LVDS Serializer in Samsung 28FDSOI
The 28FDSOI-LVDS-4CH-TX-1250-PLL is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parall...
2710
0.0
Four Channel LVDS Serializer in TSMC 130nm
The MXL-SR-LVDS-4CH7-130 is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data ...
2711
0.0
Low Power MCU I/O
This I/O library can easily support digital core voltage power off, and voltage transformation between different voltage domains. The common GPIOs con...
2712
0.0
Up to 1.25 Gbps DDR LVDS IPs library
130TSMC_LVDS_04 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Bandgap reference block (LVDS_BG)...
2713
0.0
Up to 400 Mbps DDR LVDS receiver
130GF_LVDS_01 is a LVDS receiver with data rate up to 400 Mbps (DDR mode). The LVDS receiver converts input LVDS signal to differential CMOS 1.5V stan...
2714
0.0
Special I/O-eMMC/SDIO (22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwidth capabilities, whic...
2715
0.0
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells....
2716
0.0
GPIO IP
GPIO provides general purpose input output interface with AXI, AHB, Avalon and APB, compatible with standard protocol of GPIO specifications. Through ...
2717
0.0
sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
Foundry sponsored - sROMet compiler - TSMC 55 nm HV - Non volatile memory optimized for high density and high speed - compiler range up to 2M...
2718
0.0
sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
Foundry sponsored - sROMet compiler - TSMC 55 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler ra...
2719
0.0
TSMC 40G 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G te...
2720
0.0
TSMC 40G 2Gb/s RX LVDS IO cell
The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology....
2721
0.0
TSMC 40G 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology....
2722
0.0
TSMC 40G Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/0.9V o...
2723
0.0
TSMC 40LP 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 LP t...
2724
0.0
TSMC 40LP 2Gb/s RX LVDS IO cell
The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 LP technology....
2725
0.0
TSMC 40LP 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 LP technology....
2726
0.0
TSMC 40LP Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/1.1V o...
2727
0.0
TSMC 65GP 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.0V or 1.8V/1.0V, designed on the TSMC 65 GP t...
2728
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TSMC 65GP 2Gb/s RX LVDS IO cell
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2729
0.0
TSMC 65GP 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.0V or 1.8V/1.0V, designed on the TSMC 65 GP technology....
2730
0.0
TSMC 65GP Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/1.0V o...
2731
0.0
TSMC 65LP 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP t...
2732
0.0
TSMC 65LP 2Gb/s RX LVDS IO cell
The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP technology....
2733
0.0
TSMC 65LP 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP technology....
2734
0.0
TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/1.2V o...
2735
0.0
TSMC CLN16FFC TCAM Compiler with ULVT periphery
IGMTLSV03A is a synchronous ULVT periphery high-density ternary content addressable memory (TCAM). It is developed with TSMC 16nm 0.8V/1.8V CMOS LOGIC...
2736
0.0
TSMC CLN16FFC Ultra High Density One Port Register File
IGMSLRV01A is a synchronous SVT / LVT periphery ultra high density one port register file compiler. It is developed with TSMC 16 nm 0.8 V/1.8 V CMOS L...
2737
0.0
TSMC CLN5FF High Density Single Port SRAM Compiler
IGMSHDY01A is a synchronous ULVT / LVT periphery high density single port SRAM compiler. It is developed with TSMC 5 nm 0.75 V/1.2 V CMOS LOGIC FinFET...
2738
0.0
TSMC CLN6FF Pre-search and Pipeline Ternary Content Addressable Memory Compiler
IGMTLSX08A is a synchronous LVT / ULVT periphery high-density pre-search and pipeline ternary content addressable memory (TCAM) with column redundancy...
2739
0.0
TSMC CLN6FF Ternary Content Addressable Memory Compiler with Column Redundancy
IGMTLSX07A is a synchronous LVT / ULVT periphery high-density ternary content addressable memory (TCAM) with column redundancy feature. It is develope...
2740
0.0
TSMC CLN7FF Synchronous One Port Register File Compiler
The IGMSLRX01A is a synchronous, ultra-high density one port register file compiler. It is developed with TSMC 7 nm 0.75 V/1.8 V CMOS LOGIC FinFET Pro...
2741
0.0
TSMC CLN7FF Ternary Content Addressable Memory Compiler with Column Redundancy
IGMTLSX06A is a synchronous LVT / ULVT periphery high-density ternary content addressable memory (TCAM) with column redundancy feature. It is develope...
2742
0.0
TSMC embedded flash controller
The eSi-TSMC-Flash IP core provides an AMBA 3 AHB-lite interface to TSMC's embedded flash macros....
2743
0.0
TSMC N3P 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2744
0.0
TSMC N3P Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2745
0.0
TSMC N3P Source Sync 3DIO PHY
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2746
0.0
TSMC N5 Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2747
0.0
PSRAM/SD3.0/EMMC5.1 IO in SMIC 28HKD 0.9/2.5V, upto 600Mbps
...
2748
0.0
SSTL_15_18 IO Pad Set
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since t...
2749
0.0
Asynchronous FIFO alternate design
This version of an asynchronous FIFO eschews the traditional grey code counters for a more complete and secure transfer mechanism between clock domain...
2750
0.0
Asynchronous FIFO with flags and depth counter
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