Analog & Mixed Signal IP Core

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1902

1.0

UMC L90G 90nm Deskew PLL - 180MHz-900MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1903

1.0

UMC L90G 90nm Deskew PLL - 360MHz-1800MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1904

1.0

UMC L90G 90nm Deskew PLL - 90MHz-450MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1905

1.0

UMC L90G 90nm Spread Spectrum PLL - 180MHz-900MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1906

1.0

UMC L90G 90nm Spread Spectrum PLL - 360MHz-1800MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1907

1.0

UMC L90G 90nm Spread Spectrum PLL - 90MHz-450MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1908

1.0

UMC L90GOD 90nm Clock Generator PLL - 125MHz-625MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1909

1.0

UMC L90GOD 90nm Clock Generator PLL - 250MHz-1250MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1910

1.0

UMC L90GOD 90nm Clock Generator PLL - 500MHz-2500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1911

1.0

UMC L90GOD 90nm DDR DLL - 144MHz-720MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1912

1.0

UMC L90GOD 90nm DDR DLL - 192MHz-960MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1913

1.0

UMC L90GOD 90nm Deskew PLL - 125MHz-625MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1914

1.0

UMC L90GOD 90nm Deskew PLL - 250MHz-1250MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1915

1.0

UMC L90GOD 90nm Deskew PLL - 500MHz-2500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1916

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 125MHz-625MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1917

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 250MHz-1250MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1918

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 500MHz-2500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1919

1.0

UMC L90SP 90nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1920

1.0

UMC L90SP 90nm Clock Generator PLL - 240MHz-1200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1921

1.0

UMC L90SP 90nm Clock Generator PLL - 60MHz-300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1922

1.0

UMC L90SP 90nm DDR DLL - 60MHz-300MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1923

1.0

UMC L90SP 90nm DDR DLL - 80MHz-400MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1924

1.0

UMC L90SP 90nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1925

1.0

UMC L90SP 90nm Deskew PLL - 240MHz-1200MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1926

1.0

UMC L90SP 90nm Deskew PLL - 60MHz-300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1927

1.0

UMC L90SP 90nm Spread Spectrum PLL - 120MHz-600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1928

1.0

UMC L90SP 90nm Spread Spectrum PLL - 240MHz-1200MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1929

1.0

UMC L90SP 90nm Spread Spectrum PLL - 60MHz-300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1930

1.0

1MHz Oscillator

The ll_osc1455s01_ln14lpp_34201 is a 0.8V oscillator whose output frequency (FOUT) is controlled by internal registers. The typical output frequency o...

1931

1.0

4MHz Oscillator

The ll_osc2700a01_lnf28lp_7002 is a 1.0V oscillator whose output frequency (FOUT) is controlled by internal registers. The typical output frequency ra...

1932

1.0

2MHz Ultra Low Power Oscillator - Ultra low power (720nW) Silterra 0.18 μm

This macro-cell is a general purpose, ultra low power internal oscillator core designed for SilTerra 0.18µm CL180G CMOS technology. The circuit has in...

1933

1.0

6MHz ±1% PVT 1.8V Low Power Oscillator in Silterra 0.18um

This macro-cell is a low-power, precision, general purpose 1.8V 6MHz ±1% PVT internal oscillator core aimed for clock generation. A 7 bit digital bus ...

1934

1.0

6MHz ±1% PVT 3.3V Low Power Oscillator in Silterra 0.18um

This macro-cell is a low-power, precision, general purpose 3.3V 6MHz ±1% PVT internal oscillator core aimed for clock generation. A 7 bit digital bus ...

1935

1.0

SMIC 0.11um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...

1936

1.0

SMIC 0.11um 32KHz Crystal Oscillator

Process: SMIC 0.11um Logic 1P8M 1.2V/3.3V CMOS process Operating voltage range: VCC_XO: 1.62~3.6V Operating temperature range: -40~125°C Operati...

1937

1.0

SMIC 0.13um 1.2v / 3.3v Audio PLL

This PLL is designed for audio clock generation. The reference clock is 13.5MHz crystal or the input clock. It supports both 256X and 384X oversamplin...

1938

1.0

SMIC 0.13um 1.2v 200MHz Ring Oscillator

The SMIC18_CODEC_01 specifies the design of a high-performance 16-bit stereo Audio CODEC for portable digital audio systems. The ADCs and DACs within ...

1939

1.0

SMIC 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...

1940

1.0

SMIC 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-6...

1941

1.0

SMIC 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...

1942

1.0

SMIC 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...

1943

1.0

SMIC 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for generating system clock. It contains a PFD, Charge pump, 3rd order loop filter, a 1-64 input clock d...

1944

1.0

SMIC 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for generating system clock. High speed VCO can run from 250MHz to 500MHz. By setting DM [5:0] and DN [7...

1945

1.0

SMIC 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-6...

1946

1.0

SMIC 0.13um 1.2v FN-PLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 200MHz to 500MHz. It contains a 1-64 in...

1947

1.0

SMIC 0.13um 1.2V Power On Reset

Present Power on Reset generates system reset pulses (POR12) when 1.2V power supplier (VIN12) is turned on. This IP can not operate stand-alone becaus...

1948

1.0

SMIC 0.13um 1.2V Power On Reset

Present Power on Reset generates system reset signal (POR12) when 1.2V power supplier (VIN12) is turned on. This IP can not operate stand-alone becaus...

1949

1.0

SMIC 0.13um 1.2v/3.3v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 100MHz to 300MHz (If the analog power drops...

1950

1.0

SMIC 0.13um 1.2v/3.3v PLL

This PLL is designed for audio clock generation. The reference clock is 12MHz crystal or the input clock. It supports 256*fs clock output, where fs is...

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