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5514 IP
2051
1.0
GSMC 0.18um Voltage Detector
This IP is a Voltage Detector (VDT) circuit for power management application. When the supply voltage (AVDD33) increases above the detection level (VT...
2052
1.0
GSMC 0.18um Voltage Detector
The present IP is a Voltage Detector (VDT) circuit. When the voltage is in the range of VTHL to VTHH, the output, OUT_RD, is generated as a high level...
2053
1.0
GSMC 0.18um Voltage Detector
This IP is a Voltage Detector (VDT) circuit for power management application. When the supply voltage (AVDD33) increases above the detection level (VT...
2054
1.0
GSMC 0.18¦Ìm 1.8v/3.3v Power Switch
The GSMC18_PSW_02 is a PMOS power switch between the main power supply and circuit cell. Its RON is 1ohm....
2055
1.0
GSMC 0.18μm 3.3v-1.8v Noise Current Source
GSMC18_NCS_01 is a Noise Current Source IP. It depicts a current consumption block controlled by random code to draw 0mA~3.2mA noise current consumpti...
2056
1.0
GSMC 0.18µm 5v-5v/3v/1.8v Power Regulator
This IP is a Low-Dropout (LDO) 5V to 5V/3V/1.8V power regulator in GSMC 0.18μm Logic/EFLASH process. The max rated output current of the PRG is 65mA, ...
2057
1.0
TSMC 55nm 1.0/2.5V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application. The sole power supply is 3.3V, but it can be as low as 1.6...
2058
1.0
TSMC 55nm 12-Bit 8-Input 1M/200k SAR ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core intern...
2059
1.0
TSMC 55nm Analog 2-1 MUX
This analog 2-1 MUX is designed for low speed application....
2060
1.0
TSMC 65nm 12-Bit 8-Input 1M/200k SAR ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core intern...
2061
1.0
TSMC 65nm Analog 2-1 MUX
This analog 2-1 MUX is designed for low speed application....
2062
1.0
TSMC CL013G 130nm Clock Generator PLL - 136MHz-680MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2063
1.0
TSMC CL013G 130nm Clock Generator PLL - 272MHz-1360MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2064
1.0
TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2065
1.0
TSMC CL013G 130nm DDR DLL - 107MHz-535MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2066
1.0
TSMC CL013G 130nm DDR DLL - 51MHz-255MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2067
1.0
TSMC CL013G 130nm DDR DLL - 68MHz-340MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2068
1.0
TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2069
1.0
TSMC CL013G 130nm Deskew PLL - 272MHz-1360MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2070
1.0
TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2071
1.0
TSMC CL013G 130nm General Purpose PLL - 136MHz-680MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2072
1.0
TSMC CL013G 130nm Spread Spectrum PLL - 136MHz-680MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2073
1.0
TSMC CL013G 130nm Spread Spectrum PLL - 272MHz-1360MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2074
1.0
TSMC CL013G 130nm Spread Spectrum PLL - 68MHz-340MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2075
1.0
TSMC CL013LP 130nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2076
1.0
TSMC CL013LP 130nm Clock Generator PLL - 220MHz-1100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2077
1.0
TSMC CL013LP 130nm Clock Generator PLL - 55MHz-275MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2078
1.0
TSMC CL013LP 130nm DDR DLL - 42MHz-210MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2079
1.0
TSMC CL013LP 130nm DDR DLL - 56MHz-280MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2080
1.0
TSMC CL013LP 130nm DDR DLL - 88MHz-440MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2081
1.0
TSMC CL013LP 130nm Deskew PLL - 110MHz-550MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2082
1.0
TSMC CL013LP 130nm Deskew PLL - 220MHz-1100MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2083
1.0
TSMC CL013LP 130nm Deskew PLL - 55MHz-275MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2084
1.0
TSMC CL013LP 130nm General Purpose PLL - 110MHz-550MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2085
1.0
TSMC CL013LP 130nm Spread Spectrum PLL - 110MHz-550MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2086
1.0
TSMC CL013LP 130nm Spread Spectrum PLL - 220MHz-1100MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2087
1.0
TSMC CL013LP 130nm Spread Spectrum PLL - 55MHz-275MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2088
1.0
TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2089
1.0
TSMC CL013LV 130nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2090
1.0
TSMC CL013LV 130nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2091
1.0
TSMC CL013LV 130nm DDR DLL - 139MHz-695MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2092
1.0
TSMC CL013LV 130nm DDR DLL - 66MHz-330MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2093
1.0
TSMC CL013LV 130nm DDR DLL - 88MHz-440MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2094
1.0
TSMC CL013LV 130nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2095
1.0
TSMC CL013LV 130nm Deskew PLL - 320MHz-1600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2096
1.0
TSMC CL013LV 130nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2097
1.0
TSMC CL013LV 130nm General Purpose PLL - 160MHz-800MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2098
1.0
TSMC CL013LV 130nm Spread Spectrum PLL - 160MHz-800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2099
1.0
TSMC CL013LV 130nm Spread Spectrum PLL - 320MHz-1600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2100
1.0
TSMC CL013LV 130nm Spread Spectrum PLL - 80MHz-400MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
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