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5514 IP
2251
1.0
TSMC CLN40G 40nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2252
1.0
TSMC CLN40G 40nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2253
1.0
TSMC CLN40G 40nm Deskew PLL - 170MHz-850MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2254
1.0
TSMC CLN40G 40nm Deskew PLL - 340MHz-1700MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2255
1.0
TSMC CLN40G 40nm Deskew PLL - 680MHz-3400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2256
1.0
TSMC CLN40G 40nm General Purpose PLL - 340MHz-1700MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2257
1.0
TSMC CLN40G 40nm Multi Phase DLL - 170MHz-850MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2258
1.0
TSMC CLN40G 40nm Multi Phase DLL - 340MHz-1700MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2259
1.0
TSMC CLN40G 40nm Multi Phase DLL - 680MHz-3400MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2260
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2261
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2262
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 600MHz-3000MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2263
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 150MHz-750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2264
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2265
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 75MHz-375MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2266
1.0
TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2267
1.0
TSMC CLN40LP 40nm DDR DLL - 177MHz-885MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2268
1.0
TSMC CLN40LP 40nm DDR DLL - 84MHz-420MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2269
1.0
TSMC CLN40LP 40nm Deskew PLL - 150MHz-750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2270
1.0
TSMC CLN40LP 40nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2271
1.0
TSMC CLN40LP 40nm Deskew PLL - 75MHz-375MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2272
1.0
TSMC CLN40LP 40nm General Purpose PLL - 150MHz-750MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2273
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 150MHz-750MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2274
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 300MHz-1500MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2275
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 75MHz-375MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2276
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2277
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2278
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 75MHz-375MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2279
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 130MHz-650MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2280
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 260MHz-1300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2281
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 520MHz-2600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2282
1.0
TSMC CLN55GP 55nm DDR DLL - 150MHz-750MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2283
1.0
TSMC CLN55GP 55nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2284
1.0
TSMC CLN55GP 55nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2285
1.0
TSMC CLN55GP 55nm Deskew PLL - 130MHz-650MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2286
1.0
TSMC CLN55GP 55nm Deskew PLL - 260MHz-1300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2287
1.0
TSMC CLN55GP 55nm Deskew PLL - 520MHz-2600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2288
1.0
TSMC CLN55GP 55nm General Purpose PLL - 260MHz-1300MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2289
1.0
TSMC CLN55GP 55nm Multi Phase DLL - 130MHz-650MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2290
1.0
TSMC CLN55GP 55nm Multi Phase DLL - 260MHz-1300MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2291
1.0
TSMC CLN55GP 55nm Multi Phase DLL - 520MHz-2600MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2292
1.0
TSMC CLN55GP 55nm Spread Spectrum PLL - 130MHz-650MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2293
1.0
TSMC CLN55GP 55nm Spread Spectrum PLL - 260MHz-1300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2294
1.0
TSMC CLN55GP 55nm Spread Spectrum PLL - 520MHz-2600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2295
1.0
TSMC CLN55LP 55nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2296
1.0
TSMC CLN55LP 55nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2297
1.0
TSMC CLN55LP 55nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2298
1.0
TSMC CLN55LP 55nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2299
1.0
TSMC CLN55LP 55nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2300
1.0
TSMC CLN55LP 55nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
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