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5687 IP
3101
0.118
DC-DC IP, Input: 0.95V - 1.5V, Output: 3V/100mA, UMC 0.11um HS/AE process
0.95V~1.5V to 3.0V DC-DC converter with 100mA driving capability, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
3102
0.118
DC-DC IP, Input: 2.5V - 4.2V, Output: 3.3V/50uA, HJTC 0.18um eFlash/G2 process
Input 2.5V~4.2V, Output=3.3V, Loading 50uA charge pump PWM Regulator, HJTC 0.18um eFlash 1.8V/3.3V/5V process....
3103
0.118
DC-DC IP, Input: 2.5V / 3.3V, Output: 1.05V/250mA, UMC 0.11um HS/AE process
2.5V/3.3V to 1.05V high efficiency converter with 250mA driving capability, compensation built-in, PWM regulator, UMC 0.11um HS/AE (AL Advanced Enhanc...
3104
0.118
DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process
Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0....
3105
0.118
DC-DC IP, Input: 3.3V, Output: 3.3V/300mA, UMC 0.153um MS process
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode process....
3106
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 0.11um HS/AE process
3V~3.6V to 5V DC-DC converter with 100mA driving capability, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
3107
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 40nm LP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Pulse Width Modulator, UMC 40nm Logic LP/RVT Low-K process....
3108
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 65nm SP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0, Pulse Width Modulator, UMC 65nm SP/HVT Logic Low-K process....
3109
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 90nm SP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0mA, Pulse Width Modulator, UMC 90nm SP/RVT Low-K process....
3110
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, HJTC 0.18um eFlash/G2 process
PWM charge pump with internal soft start function. The input voltage is 3.3V. The output voltage is 5V with 50mA driving, HJ 0.18um eFlash process....
3111
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.153um MS process
Pulse Width Modulation, boosting voltage from 3.3V to 5V/50mA driving capability, Ivcca=140uA@Idrive=0, UMC 0.153um Logic/Mixed-Mode process....
3112
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.18um G2 process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=140uA @ Idrive=0....
3113
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0....
3114
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 65nm LL process
DC-DC Power converter, Input:3.0V~3.6V, output:5V, 50mA loading, UMC 65nm LL/RVT Low_K process....
3115
0.118
DC-DC IP, Input: 5V, Output: 3.3V/300mA, UMC 0.11um HS/AE process
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.11um 1.2V/3.3V HS/AE (AL Advanced Enhancement) Logic process...
3116
0.118
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.2V/50mA, UMC 0.13um HS/FSG process
3.3V to 1.2V high efficiency converter with 50mA driving capability, PWM Regulator, UMC 0.13um HS/FSG Logic process....
3117
0.118
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process
3.3V to 1.8V high efficiency converter with 150mA driving capability, PWM Regulator, UMC 0.13um LL Logic/FSG process....
3118
0.118
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/200mA, with soft-start, UMC 0.13um HS/FSG process
3.3V to 1.8V high efficiency converter with 200mA driving capability PWM Regulator, UMC 0.13um HS/FSG Logic process....
3119
0.118
DC-DC IP, Step-up PWM Regulator, Input: 3.0V - 3.6V, Output: 5V/100mA, with soft-start, UMC 0.13um HS/FSG process
PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process....
3120
0.118
PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process....
3121
0.118
DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
3122
0.118
DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhanceme...
3123
0.118
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process....
3124
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic ...
3125
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process....
3126
0.118
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process....
3127
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
3128
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process....
3129
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....
3130
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....
3131
0.118
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....
3132
0.118
DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....
3133
0.118
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....
3134
0.118
DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process
Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....
3135
0.118
DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process
Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....
3136
0.118
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....
3137
0.118
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
3138
0.118
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....
3139
0.118
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....
3140
0.118
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process...
3141
0.118
OFDM AFE using UMC 55nm eFlash Process
OFDM AFE using UMC 55nm eFlash Process...
3142
0.118
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process...
3143
0.118
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process...
3144
0.118
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user...
3145
0.118
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40...
3146
0.118
Linear Regulator IP, HJTC 0.11um eFlash process
3.3V to 1.5V/150mA REG, Linear Regulator, HJTC 0.11um eFlash process....
3147
0.118
Linear Regulator IP, Input: 1.0V - 3.6V, Output: 0.9V/20mA, Standby Current: 0.8uA, UMC 55nm ULP process
1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process...
3148
0.118
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 240mA, UMC 0.18um G2 process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process....
3149
0.118
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 60mA, UMC 0.18um G2 process
3.3V with 60mA driving capability, Istb=85uA Linear Regulator, UMC 0.18um GII Logic process....
3150
0.118
Linear Regulator IP, Input: 2.0V - 3.9V, Output: 1.8V / 150mA, Iq=66uA, Idis=1uA, UMC 0.18um G2 process
3.3V with 150mA driving capability, Istb=96uA Linear Regulator, UMC 0.18um GII Logic process....
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