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5687 IP
3351
0.118
DLL IP, Input: 18MHz - 45MHz, Output: 18 - 45MHz, UMC 90nm SP process
Input 18M-45MHz, output 18M-45MHz, timing generator DLL, UMC 90nm SP/RVT Low-K process....
3352
0.118
PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process....
3353
0.118
PLL IP, Input: 20MHz - 24MHz, Output: 20MHz - 100MHz, UMC 0.5um process
Input 20M-24MHz, output 20M-100MHz, frequency synthesizable PLL, 0.5um Logic process....
3354
0.118
PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for JitteRClean Mode. UMC 4...
3355
0.118
PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process
high speed clock generator using UMC 0.13um 1.2V HS process....
3356
0.118
PLL IP, Input: 32.768KHz, Output: 12MHz - 30MHz, UMC 90nm SP process
Input 32.768KHz, output 12M-30MHz, PLL, UMC 90nm SP/RVT Logic Low-K process....
3357
0.118
PLL IP, Input: 32.768KHz, Output: 12MHz - 48MHz, UMC 0.11um HS/FSG process
Input 32.768KHz, output 12M-48MHz, PLL, UMC 0.11um HS/Copper Logic process....
3358
0.118
PLL IP, Input: 32.768KHz, Output: 12MHz, UMC 0.153um G2 process
Input 32.768KHz, output 12MHz, PLL, UMC 0.153um GII Logic/MM process....
3359
0.118
PLL IP, Input: 372M - 540MHz, Output: 5MHz - 400MHz, UMC 0.13um HS/FSG process
Input 372M ~ 540MHz, output 5M ~ 400MHz, PLL, UMC 0.13um HS/FSG Logic process....
3360
0.118
PLL IP, Input: 372M - 540MHz, Output: 5MHz - 420MHz, UMC 0.11um HS/FSG process
Input 372M ~ 540MHz, output 5M ~ 420MHz, PLL, UMC 0.11um HS/FSG Logic process....
3361
0.118
DLL IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 25% delay in period of FREF, UMC 28nm Logic and Mi...
3362
0.118
DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3363
0.118
DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process
DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process...
3364
0.118
UMC 28nm high performance stereo audio codec with highly integrated analog functionality system
UMC 28nm high performance stereo audio codec with highly integrated analog functionality system...
3365
0.118
UMC 40nm high performance mono audio codec with highly integrated analog functionality system
UMC 40nm high performance mono audio codec with highly integrated analog functionality system...
3366
0.118
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%....
3367
0.118
UMC 55uLP_x005F_x005F_x005F_x000D_ ADC
UMC 55uLP ADC...
3368
0.118
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process...
3369
0.118
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process.
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process....
3370
0.118
Analog Comparator; 0.25um Logic process
Analog Comparator; 0.25um Logic process...
3371
0.118
Analog Front End IP for CMOS image processing applications
FXAFE010HF0A is an Analog Front End IP for CMOS image processing applications. FXAFE010HF0A is fabricated in UMC 55nm SP, low-k, logic process to enab...
3372
0.118
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process...
3373
0.118
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x000D_
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process...
3374
0.118
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process...
3375
0.118
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process...
3376
0.118
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process...
3377
0.118
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process...
3378
0.118
Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process
Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process...
3379
0.118
Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process
Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process...
3380
0.118
Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40nm LP Logic Process
Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40n...
3381
0.118
Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process...
3382
0.118
Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process
Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process...
3383
0.118
Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process
Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process...
3384
0.118
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process...
3385
0.118
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process...
3386
0.118
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process_x005F_x005F_x005F_x000D_
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process...
3387
0.118
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process...
3388
0.118
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process...
3389
0.118
Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process
Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process...
3390
0.118
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process...
3391
0.118
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process...
3392
0.118
Input 20M-66M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process
Input 20M-66M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process...
3393
0.118
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process...
3394
0.118
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process...
3395
0.118
Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process.
Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process....
3396
0.118
Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process
Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process...
3397
0.118
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process....
3398
0.118
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process....
3399
0.118
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3400
0.118
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process...