Design & Reuse
arrow A/D Converter (ADC) (531)
arrow Amplifier (102)
arrow Analog Comparator (21)
arrow Analog Filter (27)
arrow Analog Front Ends (38)
arrow Analog Multiplexer (3)
arrow Analog Subsystems (3)
arrow Clock Synthesizer (83)
arrow Coder/Decoder (CODEC) (107)
arrow D/A Converter (DAC) (222)
arrow DC-DC Converter (67)
arrow DLL (743)
arrow Graphics & Video Modules (5)
arrow Oscillator (342)
arrow Oversampling Modulator (8)
arrow PLL (1723)
arrow Power Management (855)
arrow RF Modules (82)
arrow Sensor (39)
arrow Sensors and Monitors (45)
arrow Switched Cap Filter (1)
arrow Temperature Sensor (143)
arrow Other (497)
5687 IP
3401
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
3402
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
3403
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mix...
3404
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
3405
0.118
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Pr...
3406
0.118
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Process
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Pro...
3407
0.118
Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3408
0.118
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process...
3409
0.118
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic...
3410
0.118
Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process
Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm ...
3411
0.118
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process...
3412
0.118
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process...
3413
0.118
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm...
3414
0.118
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process...
3415
0.118
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process...
3416
0.118
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process....
3417
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
3418
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
3419
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...
3420
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...
3421
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process .
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...
3422
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
3423
0.118
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process....
3424
0.118
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process....
3425
0.118
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process....
3426
0.118
Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process.
Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process....
3427
0.118
Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process.
Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process....
3428
0.118
Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process...
3429
0.118
Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process...
3430
0.118
Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process...
3431
0.118
Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process...
3432
0.118
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process...
3433
0.118
Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process
Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process...
3434
0.118
Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process...
3435
0.118
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process...
3436
0.118
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process...
3437
0.118
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process...
3438
0.118
Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process...
3439
0.118
Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process
Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process...
3440
0.118
Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process
Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process...
3441
0.118
internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process
internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process...
3442
0.118
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process...
3443
0.118
Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process.
Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process....
3444
0.118
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3445
0.118
Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process
Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process...
3446
0.118
Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process
Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process...
3447
0.118
Internal-RC, trimmable fixed frequency 80MHz. Power Supply: 3V-3.6V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Internal-RC, trimmable fixed frequency 80MHz. Power Supply: 3V-3.6V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3448
0.118
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x005F_x005F_x005F_x000D_
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process....
3449
0.118
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm LP process.
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm LP process....
3450
0.118
NO External-R ,frequency 32.768KHz , Oscillator . Input 0.9V+/-10%; UMC 55nm ULP process.
NO External-R ,frequency 32.768KHz , Oscillator . Input 0.9V+/-10%; UMC 55nm ULP process....