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5593 IP
3801
0.0
UMC L40LP 40nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3802
0.0
5 GHz 250 fs jitter Phase Locked Loop IP Block
The PLL5G250F is an ultra-low power phase locked loop (PLL) intellectual property (IP) block. The PLL5G250F features a very small area footprint, w...
3803
0.0
UMC L40LP 40nm Deskew PLL - 150MHz-750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3804
0.0
IQ ADC on TSMC 130nm
10Bit 10Msps 3.3V SAR ADC...
3805
0.0
UMC L40LP 40nm Deskew PLL - 75MHz-375MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3806
0.0
General purpose voltage/current out bias on TSMC 130nm
General purpose voltage/current out bias, Vout=0.6V, Iout=20uA...
3807
0.0
General purpose Brown-out-detector on TSMC 130nm
General purpose Brown-out-detector...
3808
0.0
Crystal Oscillator 32.768kHz on TSMC 130nm
32.768kHz crystal oscillator...
3809
0.0
Temperature sensor with diode sensor on TSMC 130nm
Temperature sensor with diode sensor, range=-40~125C...
3810
0.0
Temperature sensor with digital sensor on TSMC 130nm
Temperature sensor with digital sensor, range=-40~125C...
3811
0.0
Voltage/current out bias with PTAT on TSMC 28nm
Voltage/current out bias with PTAT, Vout=0.3~0.6V, Iout=10~40uA...
3812
0.0
General purpose Brown out detector -BOD on TSMC 28nm
General purpose Brown-out-detector...
3813
0.0
Core voltage Power on reset - POR on TSMC 28nm
Core voltage Power-on-reset...
3814
0.0
IO voltage Power on reset POR on TSMC 28nm
IO volrage Power-on-reset...
3815
0.0
RC Oscillator_16MHz on TSMC 28nm
16MHz Internal RC OSC...
3816
0.0
UMC L55LP 55nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3817
0.0
RC Oscillator_32.768KHz on TSMC 28nm
32.768KHz Internal RC OSC...
3818
0.0
Temperature sensor with diode sensor -TMUA on TSMC 28nm
Temperature sensor with diode sensor, range=-40~125C...
3819
0.0
Temperature sensor with digital sensor -TMUD on TSMC 28nm
Temperature sensor with digital sensor, range=-40~125C...
3820
0.0
40 mA LDO voltage regulator (3.3/5.0V to 1.8V)
180TSMC_LDO_20 is LDO to convert IO voltage 3.0V÷5.5V to 1.8V and designed to supply integrated circuits with stable and precise voltage with load up...
3821
0.0
On-Chip IO to Core Voltage Buck Regulator
The OT1153 series on-chip regulators allow for efficient on-chip conversion of IO voltages to Core voltages. E.g. 3.3V to 1.2V with only one external ...
3822
0.0
GF L013N 130nm DDR DLL - 68MHz-340MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
3823
0.0
TSMC CLN6FF 6nm Spread Spectrum PLL - 175MHz-875MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3824
0.0
UMC L55LP 55nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3825
0.0
PVT Sensor - TSMC 16 FFC
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
3826
0.0
PVT Sensor - TSMC 12 FFC
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
3827
0.0
PVT Sensor - TSMC 28 HPC+
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
3828
0.0
PVT Sensor - TSMC 40
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
3829
0.0
Low Dropout (LDO) Capless Regulator 250mA - TSMC 28 HPC+
1-VIA’s Linear Low-Dropout (LDO) voltage regulator IP is a capless LDO regulator which provides programmable precise voltage regulation across a wide ...
3830
0.0
Low Dropout (LDO) Capless Regulator 250mA - TSMC 40
1-VIA’s Linear Low-Dropout (LDO) voltage regulator IP is a capless LDO regulator which provides programmable precise voltage regulation across a wide ...
3831
0.0
16bit 100Ksps Sigma Delta ADC in 130nm~22nm
This IP include a PGA and a delta-sigma ADC, can be used in various sensor measurement....
3832
0.0
16bit 3Msps Sigma Delta ADC in 130nm~22nm
This IP is an 16-bit resolution sigma-delta ADC, can be used in various sensor measurement....
3833
0.0
12bit R2R DAC
This IP is a 12-bit resolution, 1MHz convert rate R2R DAC on 180nm~ 12nm process. The internal DAC includes data latch circuits, R2R ladder and output...
3834
0.0
100nA Ultra-low Power LDO in 110nm~12nm
The LDO IP supports various input voltage ranges include 1.90V~3.60V, 1.90V~5.50V and so on. The typical output voltage of this LDO can be configratio...
3835
0.0
UMC L55LP 55nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3836
0.0
UMC L65LP 65nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3837
0.0
UMC L65LP 65nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3838
0.0
UMC L65LP 65nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3839
0.0
GF L28HPP 28nm Deskew PLL - 700MHz-3500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3840
0.0
GF L28HPP 28nm Deskew PLL - 350MHz-1750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3841
0.0
12-bit, 9.2 GSPS Analog-to-Digital Converter
The A12B9G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a time-interleaved successive a...
3842
0.0
11-bit, 5 GSPS Analog-to-Digital Converter
The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a hybrid successive approxima...
3843
0.0
12-bit, 200 MSPS Analog-to-Digital Converter IP Block
The A12B200M is a low-power, analog to digital converter (ADC) intellectually property (IP) design block. It is a hybrid successive approximatio...
3844
0.0
GF L28HPP 28nm Deskew PLL - 175MHz-875MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3845
0.0
GF L28SLP 28nm Deskew PLL - 440MHz-2200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3846
0.0
GF L28SLP 28nm Deskew PLL - 220MHz-1100MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3847
0.0
GF L28SLP 28nm Deskew PLL - 110MHz-550MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3848
0.0
GF L55G 55nm Deskew PLL - 360MHz-1800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3849
0.0
GF L55G 55nm Deskew PLL - 180MHz-900MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3850
0.0
GF L55G 55nm Deskew PLL - 90MHz-450MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...