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5592 IP
4051
0.0
NFC Power Management Unit (0.6/1.2/1.5 V output voltage, 10/20/50 uA output current, 2 MHz output clock frequency)
130GF_PMU_02 is a Power Management Unit (PMU) block designed to supply embedded integrated circuits with stable and precise voltage and current. IP sh...
4052
0.0
UHF RFID EPC Gen2 physical interface
130GF _G2PHY_02 is the IP intended for use in passive UHF transponder applications. IP derives its operating power from an RF electromagnetic field ge...
4053
0.0
20 mA LDO voltage regulator (output voltage 1.1V/1.2V/1.3V/1.4V)
055TSMC_LDO_09 IP is cap-based LDO voltage regulator designed to convert IO voltage 2.5V to 1.2V and supply analogy circuits with load up to 20mA. The...
4054
0.0
20 to 50 MHz crystal oscillator
055TSMC_OSC_01 is a reference frequency generator designed to form a reference signal in the frequency range from 10 to 50MHz. The block consists of a...
4055
0.0
10MHz to 50MHz Fractional-N Phase-Locked Loop
APLL Fractional-N phase locked loop frequency synthesizer is intended for SoC clock generation and embeds a reference 10MHz – 50MHz XTAL oscillator,...
4056
0.0
5mA LDO voltage regulator (output voltage value 1.15V/1.2 V/1.25V/1.3V) with BG (0.6V) and I2V (5uA, 10uA, 20uA, 50uA)
130GF_LDO_03 is a Power management unit, designed to supply integrated circuits with stable and precise voltage. IP includes Bandgap block (BG), Volta...
4057
0.0
20mA low noise LDO voltage regulator (output voltage 1.1V/1.2V/1.3V/1.4V)
055TSMC_LDO_08 IP is low noise cap-based LDO voltage regulator designed to convert IO voltage 2.5V to 1.2V and supply analogy circuits with load up to...
4058
0.0
32.768 kHz crystal oscillator
055SMIC_OSC_01 is a reference frequency generator, designed to form a reference signal with the precise frequency 32.768kHz. The oscillator is a CMO...
4059
0.0
5 MHz RC oscillator
055SMIC_OSC_02 is a low power RC oscillator nominally operates at 5MHz output clock from a 1.2V supply. The oscillator operates in a voltage range of ...
4060
0.0
12-bit 1-channel up to 100kSPS low power SAR ADC
130GF_ADC_01 is a 12 bit, 1-channel, low power SAR ADC with sampling rates up to 100 kSPS. The ADC has two operating modes: single-shot conversion a...
4061
0.0
20mA and 500mA LDO voltage regulators (output voltage 2.5V)
055TSMC_LDO_06 is a cap-based LDO voltage regulator designed to supply integrated circuits with stable and precise voltage. 2.5V. The LDO converts IO ...
4062
0.0
24-bit 1-channel 44.1 to 48kSPS delta-sigma ADC
180XFAB_ADC_01 is a 24-bit delta-sigma ADC with sampling rates from 44.1kSPS to 48kSPS. Two second order feedforward modulators are used to create f...
4063
0.0
5.8GHz Fractional-N PLL synthesizer
130GF_PLL_02 is intended for SoC clock generation with support of BFSK modulation up to 4Mbps output data rate. PLL IP block embeds a reference 8MHz/1...
4064
0.0
3.3V to 2.5V 50mA LDO voltage regulator
028SAM_LDO_05 is external-capacitor-based Linear Regulator in Samsung 28 LPP to generate SoC voltage supply voltage. The block provided with stable an...
4065
0.0
14-bit 1-channel 40 to 125 MSPS pipelined ADC
055TSMC_ADC_15 is a high-speed 14-bit ADC, employs a high-performance differential pipeline architecture. This ADC consist of 14-bit pipelined ADC cor...
4066
0.0
27.12 MHz crystal oscillator
180TSMC_OSC_05 is a reference frequency generator designed to form a 27.12 MHz reference signal. The reference signal indicator informs the control sy...
4067
0.0
1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop
180TSMC_PLL_10 is designed to generate a high frequency signal in a range from 1GHz to 3GHz and a low frequency clock signal in a range from 6MHz to 1...
4068
0.0
JTAG 2-Wire to 4-Wire Adapter
The OT4001_cjtag is an adapter which permits legacy IEEE 1149.1 ports to communicate as an IEEE 1149.7 2-wire OScan1 cJTAG port. A simple update to a ...
4069
0.0
Combined Voltage and Current Reference
The OT0118 is a medium precision, trimmed bandgap voltage reference and temperature compensated current reference generator....
4070
0.0
UMC L40G 40nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4071
0.0
UMC L40G 40nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4072
0.0
UMC L40G 40nm DDR DLL - 150MHz-750MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4073
0.0
PVT - Process, Voltage, and Temperature Monitor with Interrupt 7nm/6nm
The ODT-PVT-ULP-001C-7 is an ultra-low power temperature, voltage and process monitor designed in a 7nm/6nm CMOS process. This IP operates over the en...
4074
0.0
Low Dropout (LDO) Capless Regulator
The ODT-LDO-IC-300M-7 is a low dropout (LDO), linear regulator for integration in a SoC. The LDO uses advanced control techniques to achieve excellent...
4075
0.0
UMC L40LP 40nm DDR DLL - 177MHz-885MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4076
0.0
1MHz-50GHz Programmable Prescaler - Divider by 1/2/4/8/16 in SiGe
The PMCC_DIV50G1_16 is a high speed (up to 50GHz) fully differential programmable divider IP block, designed using Jazz SiGe120 (SBC18HX) technology. ...
4077
0.0
24GHz VCO in SiGe
The PMCC_VCO20G /24G /25G /26G /30G is a set of fully differential high speed VCOs covering 20GHz … 30GHz frequency range, designed using Jazz SiGe1...
4078
0.0
Band-gap Reference in GF N65 LP. Multiple voltages referenced to internal and external resistors.
The PMCC_REFS IP block combines two modules of GM current references and one module of BG (band-gap) current reference. Each module provides up to twe...
4079
0.0
Differential CML 50 Ohm terminated output Buffer for up to 12Gb/s (GF N65)
The PMCC_OBUF12G is a differential CML 50Ω terminated output driver for datarates from DC up to 12Gb/s. The buffer can also be used for up to 8GHz ...
4080
0.0
UMC L40LP 40nm DDR DLL - 112MHz-560MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4081
0.0
UMC L40LP 40nm DDR DLL - 84MHz-420MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4082
0.0
UMC L55LP 55nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4083
0.0
Low Dropout (LDO) Capless Regulator 250mA - TSMC 7FF
1-VIA’s Linear Low-Dropout (LDO) voltage regulator IP is a capless LDO regulator which provides programmable precise voltage regulation across a wide ...
4084
0.0
UMC L55LP 55nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4085
0.0
UMC L55LP 55nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4086
0.0
UMC L65LP 65nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4087
0.0
UMC L65LP 65nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4088
0.0
UMC L65LP 65nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4089
0.0
GF L28HPP 28nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4090
0.0
GF L28HPP 28nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4091
0.0
GF L28HPP 28nm DDR DLL - 150MHz-750MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4092
0.0
GF L28SLP 28nm DDR DLL - 246MHz-1230MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4093
0.0
GF L28SLP 28nm DDR DLL - 156MHz-780MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4094
0.0
GF L28SLP 28nm DDR DLL - 117MHz-585MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4095
0.0
GF L55G 55nm DDR DLL - 196MHz-980MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4096
0.0
GF L55G 55nm DDR DLL - 124MHz-620MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4097
0.0
GF L55G 55nm DDR DLL - 93MHz-465MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4098
0.0
GF L55LP 55nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4099
0.0
GF L55LP 55nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4100
0.0
GF L55LP 55nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...