Design & Reuse
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54 IP
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Bunch of Wires [BoW] PHY IP
Blue Cheetah's Bunch of Wires [BoW] PHY IP design incorporates the maximum benefit of the Open Compute Project's (OCP) inter-chiplet PHY spec...
52
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Nutcracker XSR Connectivity Chiplet
Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...
53
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CXL (Compute eXpress Link) 3.1 IP
The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch. The IP supports all features of the CXL 3...
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CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...