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122 IP
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40G Ultralink D2D PHY for TSMC N3P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
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40G Ultralink D2D PHY for TSMC N5P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
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40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
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D2D (Die-to-Die) Interconnect IP in WhiteBox, Unlimited Usage
This die-to-die interconnect IP Core is defined as an AIB IP Core, which is optimized for 32-bit AXI data transfer, enabling Master-to-Slave AXI trans...
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D2D PHY, ADVANCED PACKAGE, 3nm
The InPsytech (IPT) D2D PHY IP is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed...
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D2D PHY, ADVANCED PACKAGE, 5nm/4nm
The InPsytech (IPT) D2D PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and eff...
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D2D PHY, ADVANCED PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
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D2D PHY, STANDARD PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
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32G UCIe Standard PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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16G UCIe Advanced PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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16G UCIe Advanced PHY for TSMC N4P/N5P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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16G UCIe Standard PHY for Samsung SF5A
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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16G UCIe Standard PHY for TSMC N3A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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16G UCIe Standard PHY for TSMC N4P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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16G UCIe Standard PHY for TSMC N5A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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16G UCIe Standard PHY for TSMC N7
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
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UCIe Controller for Streaming Protocols
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
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UCIe PHY IP on TSMC N3P
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
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UCIe PHY on Samsung SF5A
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
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UCIe PHY on TSMC N3E
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
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UCIe Protocol Layer: AXI-S
The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Streaming AXI Bus and the FDI interface of the UCIe D2D Adapter. It allows for...
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UCIe Standard Package PHY on Samsung S14LPP
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...
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UCIe Standard Package PHY on Samsung S8LPU
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...
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UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
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UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
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UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
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UCIE-A PHY, 5nm/4nm
The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...
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UCIE-A PHY, ADVANCED PACKAGE
The InPsytech (IPT) UCIe-A PHY is a state-of-the-art physical layer interface, offering industry-leading power efficiency and proven in mass productio...
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UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
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UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
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Network Interconnect IP
The Network Interconnect (NIC) IP is a silicon proven and highly scalable on-chip communication fabric, enabling seamless connectivity between CPUs, G...
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Chiplet Solution
Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...
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Die-to-Die PHY
Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging ...
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FlexNoC 5 Network-on-Chip (NoC)
Arteris FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of sy...
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FlexNoC Resilience Package
For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required t...
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FlexWay Interconnect IP
FlexWay 5 from Arteris is an essential entry-level IP generator for cost-efficient, high-performance network-on-chip (NoC) designs. It revolutionizes ...
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GLink AXI Wrapper
GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface and provide data bus ...
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GLink CXS-Bridge
GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer and provides AMBA CXS...
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GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...
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GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...
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Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
iNoCulator is a cloud-active EDA tool that is used to define the topology of a NoC quickly and easily, configure its parameters and simulate it to mea...
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Ultra Accelerator Link（UALink) Controller
Full-stack, scalable, configurable UALink Transaction Layer (TL), Data Link Layer (DL), and Physical Layer (PL), interconnect IP for next-generation A...
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Blumind Chiplet
Contact us to learn more about Neural Signal Processor known-good-die for system in package integration....
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UMI™ for Die-to-Memory (D2M) PHY IP
Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutions....
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Universal Chiplet Interconnect Express PHY IP GlobalFoundries® 22FDX®
The Racyics UCIe PHY is an energy-efficient chiplet interconnect IP solution for consumer and automotive applications. Implemented in 22FDX technology...
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Innovative Ultra-High-Speed Chiplet Solution
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chip...
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Interconnect fabric IP with cache coherence support
StarNoC-500 is StarFive's first self-developed interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC...
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Interconnect fabric IP with cache coherence support
StarNoC-700 is StarFive's self-developed high-scalable, high-performance interconnect fabric IP supporting cache coherence, enabling the construction ...
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Interconnect Technology
EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC applicatio...
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Interface Controller - PHY IP
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...