1 100.0

UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect Blue Cheetah is a leader in Die-to-Die (D2D) interconnect solutions for chiplets in very advanced and low-cost packaging applications. BlueLynx™ is a...

2 100.0

UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3 100.0

UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

4 100.0

UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

5 100.0

Universal Chiplet Interconnect Express (UCIe) Controller Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...

6 70.0

40G UCIe PHY IP on Samsung SF4X Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

7 50.0

40G UCIe PHY for organic substrate standard packages Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

8 50.0

40G UCIe PHY for high-density advanced packages Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...

9 38.0

UCIe Die-to-Die Controller GammaCORE is a highly configurable and customizable Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP implementing the latest UC...

10 30.0

Universal Chiplet Interconnect Express (UCIe) Controller Integrating multiple chiplets within a single package has become crucial for high-performance computing. CoMira’s UCIe (Universal Chiplet Interconnect...

11 14.0

40G Ultralink D2D PHY for Samsung 7LPP Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

12 14.0

40G Ultralink D2D PHY for GF12LP+ Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

13 14.0

UltraLink Controller Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a pro...

14 14.0

Universal Chiplet Interconnect Express (UCIe 1.0) Controller Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...

15 11.0

Die-to-Die (D2D) Interconnect Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...

16 10.0

UCIe Die-to-Die Chiplet Controller Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...

17 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

18 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

19 10.0

Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5) The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale ...

20 10.0

Die-to-Die Controller IP The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...

21 10.0

UCIe D2D Adapter The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer a...

22 8.0

TSMC CLN5FF Glink 2.0 Die-to-Die PHY IGAD2DY01A is a high speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions：Integrated Fan-Out (InFO) with RDL ...

23 8.0

TSMC CLN6FF/7FF Die-to-Die Interface PHY This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP deta...

24 3.0

<4Gbps Low Power D2D Interface Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard...

25 0.0

Chiplet Solution Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...

26 0.0

Low Power Dual PHY for UCIe low cost robust Chiplets YorChip UniPHY™ Dual PHY is a flexible version of YorChip’s multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY’s unique feature ...

27 0.0

GLink Multi-Slice PCS GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...

28 0.0

GLink AXI Wrapper GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface and provide data bus ...

29 0.0

GLink CXS-Bridge GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer and provides AMBA CXS...

30 0.0

GLink Multi-Slice PCS GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...

31 0.0

TSMC CLN5FF GLink 2.3LL Die-to-Die PHY IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL...

32 0.0

TSMC CLN5FF GLink GPIO IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initiali...

33 0.0

TSMC CLN5FF GLink 2.0 Die-to-Die PHY IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL ...

34 0.0

TSMC CLN5FF GLink-3D Die-to-Die Master PHY IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY. It is used to transmit data between dies and assembled using TSMC System on Integ...

35 0.0

TSMC CLN7FF GLink-3D Die-to-Die Slave PHY IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY. It is used to transmit data between dies and assembled using TSMC System on Integr...

36 0.0

UCIe PHY on TSMC N3E Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

37 0.0

TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY IGPD2DZO1A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions, Integrated Fan-Out (InFO) with the ...

38 0.0

UCIe PHY on Samsung SF5A Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

39 0.0

16G UCIe Standard PHY for TSMC N7 UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

40 0.0

16G UCIe Standard PHY for TSMC N5A Automotive UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

41 0.0

16G UCIe Standard PHY for TSMC N4P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

42 0.0

16G UCIe Standard PHY for TSMC N3A Automotive UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

43 0.0

16G UCIe Standard PHY for Samsung SF5A UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

44 0.0

16G UCIe Advanced PHY for TSMC N3P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

45 0.0

16G UCIe Advanced PHY for TSMC N4P/N5P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

46 0.0

32G UCIe Standard PHY for TSMC N3P UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...

47 0.0

40G Ultralink D2D PHY for TSMC N6, N7 Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

48 0.0

40G Ultralink D2D PHY for TSMC N5P Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

49 0.0

40G Ultralink D2D PHY for TSMC N3P Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...

50 0.0

UCIe 1.1 PHY 5nm The UCI Express Specification Revision 1.1 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...