1 65.0

MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7 The MXL-CDPHY-4p5G-CSI-2-RX-T-N7FF is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...

2 50.0

MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is ava...

3 50.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

4 40.0

MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL The MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

5 35.0

MIPI D-PHY DSI RX (Receiver) in GlobalFoundries 22FDX The MXL-DPHY-DSI-RX-GF-22FDX is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification f...

6 30.0

MIPI D-PHY Universal IP in UMC 28HPC+ The MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...

7 25.0

MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm The MXL-DPHY-0p2G-CSI-2-TX-T-180BCD is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard ...

8 20.0

MIPI D-PHY DSI RX (Receiver/Peripheral) in UMC 22ULP/22ULL The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...

9 20.0

MIPI D-PHY TX Silicon Library's MIPI DPHY 1.2 Tx PHY IP supports data rates up to 1.5Gbps and 2.5Gbps per lane (in HS), depending on the technology node. This sili...

10 20.0

MIPI D-PHY RX Silicon Library's MIPI DPHY 1.2 Rx PHY IP supports data rates up to 1.5Gbps. This IP includes two PLLs. This silicon proven IP is available in variou...

11 20.0

MIPI D-PHY Bidirectional 2 Lanes in GF (40nm, 28nm, 22nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

12 20.0

MIPI D-PHY Bidirectional 2 Lanes in SMIC (40nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

13 20.0

MIPI D-PHY Bidirectional 2 Lanes in TSMC (40nm, 28nm, 16nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

14 20.0

MIPI D-PHY Bidirectional 4 Lanes in GF (40nm, 28nm, 22nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

15 20.0

MIPI D-PHY Bidirectional 4 Lanes in Fujitsu (40nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

16 20.0

MIPI D-PHY Bidirectional 4 Lanes in SMIC (40nm, 28nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

17 20.0

MIPI D-PHY Bidirectional 4 Lanes in TSMC (40nm, 28nm, 16nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

18 20.0

MIPI D-PHY Rx-Only 2 Lanes in GF (28nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

19 20.0

MIPI D-PHY Rx-Only 2 Lanes in SMIC (40nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

20 20.0

MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

21 20.0

MIPI D-PHY Rx-Only 2 Lanes in UMC (28nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

22 20.0

MIPI D-PHY Rx-Only 4 Lanes in GF (28nm, 12nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

23 20.0

MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

24 20.0

MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

25 20.0

MIPI D-PHY Rx-Only 4 Lanes in UMC (28nm, 22nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

26 20.0

MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

27 20.0

MIPI D-PHY Tx-Only 4 Lanes in GF (12nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

28 20.0

MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

29 20.0

MIPI D-PHY Tx-Only 4 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

30 20.0

MIPI D-PHY Tx-Only 4 Lanes in UMC (28nm, 22nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

31 10.0

MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP The MXL-CDPHY-2L-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, sourcesynchronous, physical Layer supporting the MIPI Alliance Specificatio...

32 6.0

MIPI Rx D-PHY ...

33 1.0

MIPI UniPro Controller - v1.6 To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open...

34 1.0

MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI) The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...

35 1.0

MIPI C-PHY TX PHY The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...

36 1.0

MIPI C/D-PHY TX The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...

37 1.0

MIPI D-PHY TX The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...

38 1.0

MIPI D-PHY TX COMBO LVDS PHY The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...

39 1.0

MIPI D-PHY TX Combo TTL PHY The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...

40 1.0

MIPI D-PHY_2.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

41 1.0

MIPI D-PHY_1.2G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

42 1.0

MIPI D-PHY_1.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

43 1.0

MIPI D-PHY_4.5G CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...

44 1.0

MIPI D-PHY CSI-2 RX IP Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...

45 1.0

MIPI D-PHY Combo LVDS CSI-2 RX IP Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...

46 1.0

MIPI DPHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...

47 1.0

MIPI D-PHY DSI 1.2G RX IP Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...

48 1.0

MIPI D-PHY DSI 1.5G RX IP Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...

49 1.0

MIPI D-PHY DSI TX IP Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...

50 1.0

MIPI D-PHY Combo LVDS DSI TX IP Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...