1 100.0

VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...

2 100.0

VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...

3 100.0

VESA DSC (Display Stream Compression) 1.2b Video Encoder ...

4 100.0

VESA DSC (Display Stream Compression) 1.2b Video Decoder ...

5 100.0

ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to ...

6 100.0

VDC-M (VESA Display Compression-M) Encoder The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...

7 100.0

VDC-M (VESA Display Compression-M) Decoder The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...

8 100.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...

9 100.0

VESA DSC 1.2b Encoder for Xilinx FPGAs ...

10 100.0

VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs ...

11 40.0

DP/eDP1.4b RX PHY Silicon Library's eDP/DP1.4b RX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...

12 40.0

DP/eDP1.4b TX PHY Silicon Library's eDP/DP1.4b TX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...

13 35.0

VESA VDC-M V1.2 Decoder Embrace the future of digital media with Arasan's VESA VDC-M v1.2 Decoder. Our groundbreaking product revolutionizes video compression technology, off...

14 26.0

DisplayPort 1.4a IP Core DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, ...

15 26.0

VESA Display Stream Compression (DSC) IP Core Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resol...

16 23.0

Display Stream Compression (DSC 1.2) Decoder The Trilinear Technologies Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions fro...

17 23.0

Display Stream Compression (DSC 1.2) Encoder The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K....

18 23.0

MST Topology Management Stack The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development...

19 23.0

DisplayPort Transmitter Link Controller Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link r...

20 23.0

DisplayPort Receiver Link Controller Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rate...

21 15.0

DP/eDP1.4b RX Controller Silicon Library’ｓeDP/DP1.4b RX Controller works with PHY IPs by Silicon Library or customers' PHYs....

22 15.0

DP/eDP1.4b TX Controller Silicon Library’ｓeDP/DP1.4b TX Controller works with PHY IPs by Silicon Library or customers' PHYs....

23 13.0

VESA VDC-M Decoder The Video Electronics Standards Association (VESA®) introduced the VESA Display Compression-M (VDC-M) standard, a new display interface compression st...

24 10.0

DisplayPort TX IP for high-bandwidth applications (12nm, 16nm, 28nm) M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...

25 10.0

M31 DisplayPort RX IP in 6/7nm,12/16nm, 22nm M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...

26 10.0

VESA DSC Encoder and Decoder IP Solutions Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-definition displa...

27 8.0

Scalable Ultra-High Throughput DSC 1.2b Encoder The UHT-DSC-E core is a scalable, ultra-high throughput, advanced DSC 1.2b encoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...

28 8.0

Scalable Ultra-High Throughput DSC 1.2b Decoder The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...

29 4.0

DisplayPort Transmitter & Receiver Logic Fruit Technologies has designed & implemented DISPLAY PORT Transmitter & Receiver IP Cores supporting multiple line rates up to 8.1Gbps. The IP ...

30 1.0

DP1.1 RX PHY Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...

31 1.0

DP1.2 RX PHY Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...

32 1.0

DP1.2 Transmitter PHY_40nm Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. Inn...

33 1.0

DP1.4 Receiver Controller This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....

34 1.0

DP/eDP1.4/1.2 RX PHY Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...

35 1.0

DP1.4 TX PHY Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...

36 1.0

DP/eDP1.4/1.2 TX PHY&controller Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...

37 1.0

eDP1.4 Transmitter PHY Innosilicon eDP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...

38 0.0

Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) ...

39 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+ Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...

40 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC The capacity of the Display Port 1.4 Rx IP Channel is supported. Up to 5.4bps per channel (HBR2), programmable analogue parameters like CDR Bandwidth,...

41 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth, Equalizer Strength, ...

42 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+ The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). built-in equalizer with programmable analogu...

43 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). built-in equalizer with programmable analogu...

44 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2). programmable analogue fea...

45 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP The Display Port 1.4 Rx IP Channel's maximum capacity is supported. Programmable analogue parameters including CDR Bandwidth, Equalizer Strength, Term...

46 0.0

Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm) Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...

47 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2). Integrated 100-ohm termination resistors, a bu...

48 0.0

VDC-M 1.2 Decoder The BTREE VDC-M 1.2 Decoder IP Core fully complies with VESA VDC-M 1.2 (Display Compression). Its visually lossless compression performance is up to 5...

49 0.0

VDC-M 1.2 Encoder The BTREE VDC-M 1.2 Encoder IP Core fully complies with VESA VDC-M 1.2(Display Compression). Its visually lossless compression performance is up to 5:...

50 0.0

eDisplayPort v1.4 Receiver Controller IP Core This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. ...