1 100.0

VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...

2 100.0

VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...

3 100.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...

4 40.0

DP/eDP1.4b RX PHY Silicon Library's eDP/DP1.4b RX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...

5 40.0

DP/eDP1.4b TX PHY Silicon Library's eDP/DP1.4b TX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...

6 26.0

DisplayPort 1.4a IP Core DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, ...

7 23.0

MST Topology Management Stack The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development...

8 23.0

DisplayPort Transmitter Link Controller Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link r...

9 23.0

DisplayPort Receiver Link Controller Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rate...

10 15.0

DP/eDP1.4b RX Controller Silicon Library’ｓeDP/DP1.4b RX Controller works with PHY IPs by Silicon Library or customers' PHYs....

11 15.0

DP/eDP1.4b TX Controller Silicon Library’ｓeDP/DP1.4b TX Controller works with PHY IPs by Silicon Library or customers' PHYs....

12 10.0

DisplayPort TX IP for high-bandwidth applications (12nm, 16nm, 28nm) M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...

13 10.0

M31 DisplayPort RX IP in 6/7nm,12/16nm, 22nm M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...

14 4.0

DisplayPort Transmitter & Receiver Logic Fruit Technologies has designed & implemented DISPLAY PORT Transmitter & Receiver IP Cores supporting multiple line rates up to 8.1Gbps. The IP ...

15 1.0

DP1.1 RX PHY Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...

16 1.0

DP1.2 RX PHY Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...

17 1.0

DP1.2 Transmitter PHY_40nm Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. Inn...

18 1.0

DP1.4 Receiver Controller This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....

19 1.0

DP/eDP1.4/1.2 RX PHY Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...

20 1.0

DP1.4 TX PHY Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...

21 1.0

DP/eDP1.4/1.2 TX PHY&controller Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...

22 1.0

eDP1.4 Transmitter PHY Innosilicon eDP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...

23 0.0

Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) ...

24 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+ Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...

25 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC The capacity of the Display Port 1.4 Rx IP Channel is supported. Up to 5.4bps per channel (HBR2), programmable analogue parameters like CDR Bandwidth,...

26 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth, Equalizer Strength, ...

27 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+ The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). built-in equalizer with programmable analogu...

28 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). built-in equalizer with programmable analogu...

29 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2). programmable analogue fea...

30 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP The Display Port 1.4 Rx IP Channel's maximum capacity is supported. Programmable analogue parameters including CDR Bandwidth, Equalizer Strength, Term...

31 0.0

Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm) Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...

32 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2). Integrated 100-ohm termination resistors, a bu...

33 0.0

eDisplayPort v1.4 Receiver Controller IP Core This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. ...

34 0.0

eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit ...

35 0.0

eDisplayPort v1.4 Transmitter Controller IP Core This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specification. It can be imp...

36 0.0

Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). Common-mode biassing of the CDR bandw...

37 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP The maximum capacity of the Display Port 1.4 Rx IP Channel is supported. Up to 5.4bps per channel, programmable analogue settings such as CDR Bandwidt...

38 0.0

eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption. It serves as a multi-giga...

39 0.0

eDP v1.5a RX PHY 14nm The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...

40 0.0

eDP v1.5a RX PHY 14nm The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...

41 0.0

Display Port Receiver IP Display Port Receiver core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to a w...

42 0.0

Display Port Transmitter IP Display Port Transmitter core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to ...

43 0.0

eDP Receiver IP eDP Receiver core is compliant with standard eDP 1.4b specification. Through its compatibility, it provides a simple interface to a wide range of low-...

44 0.0

eDP Transmitter IP eDP Transmitter core is compliant with standard eDP 1.4b specification. Through its compatibility, it provides a simple interface to a wide range of l...