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1890 IP
501
6.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
502
6.5077
MIPI D-PHY TRx (5nm)
The MIPI D-PHY IP is a hardmacro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. Extensive built-in self test features such as loop...
503
6.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
504
6.5077
MIPI D-PHY TRx 2.5Gbps (11nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
505
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
506
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
507
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
508
6.5077
MIPI D-PHY TRx 2.5Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
509
6.5077
MIPI D-PHY TRx 4.5Gbps (5nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
510
6.5077
MIPI D-PHY TRx 4.5Gbps (8nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
511
6.5077
MIPI DSI-2 RX Controller
The Display Serial Interface 2 (DSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance ...
512
6.5077
MIPI DSI-2 TX Controller
The Display Serial Interface 2 (DSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allian...
513
6.5077
USB Super Speed+ PHY (4nm)
The USB PHY IP consists of a hard macro PMA and soft macro PCS compliant with USB 3.2 specification, supporting SuperSpeed+ (10 Gbps) operation. This ...
514
6.5077
Multi-Standard SerDes PHY (4nm)
The MSS PHY IP consists of a hard macro PMA architecture supporting multi-standard NRZ signaling up to 20 Gbps, compliant with PCIe Gen4, DisplayPort ...
515
6.0
A 32Gbps SerDes PHY in GlobalFoundries 22FDX
This 32 Gbps SerDes PHY is implemented in GlobalFoundries 22FDX CMOS technology and provides a high-performance, protocol-agnostic serial interface fo...
516
6.0
I2C Master/Slave Controller Core IP
I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer...
517
6.0
RapidIO PHY
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the nee...
518
6.0
AHB To PCI Wrapper
VinChip’s AHB to PCI wrapper can be used to verify AHB (AMBA) based systems on a PCI environment for ease of debugging the target hardware and it can ...
519
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
520
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
521
6.0
MIPI Rx D-PHY
...
522
6.0
Embedded Host Controller 1. 1
...
523
6.0
Embedded Host Controller 2.0
...
524
6.0
USB 1.1 Hub Controller
...
525
6.0
USB 1.1 Open Host Controller
...
526
6.0
USB 2.0 Device Controller (IF Certified)
...
527
6.0
USB 2.0 Host Controller (EHCI)
...
528
6.0
USB 2.0 PHY; SMIC 40nm LL
...
529
6.0
USB 2.0 PHY; SMIC 55nm LL
...
530
6.0
USB 3.0 Device
A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of...
531
6.0
USB based High Speed System Debug IP
Architecture Independent Design Supports any AMBA AHB based System Easily portable to other buses such as Avalon Standard USB 2.0 interface to th...
532
6.0
USB2.0 On-The-Go
VinChip’s USB 2.0 High Speed OTG controller is designed for flexibility and ease of use and facilitates implementation of a wide variety of applicatio...
533
6.0
AXI- Interconnect : Advanced Extensible Interface Bus IP
The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-...
534
5.5077
112Gb/s PAM4 SERDES PHY (14nm)
The Ethernet PHY IP is used for CEI-112G applications and serializes 8b/10b encoded data for Gen1 and Gen2, as well as 128b/130b encoded data for Gen3...
535
5.5077
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
536
5.5077
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
537
5.5077
eDP v1.5a RXPHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core IP ...
538
5.5077
MIPI D-PHY TRx 2.15Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.15Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provi...
539
5.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
540
5.5077
SLVS-EC 2.0 RX PHY (14nm)
The SLVS-EC Receiver PHY IP consists of a hard macro architecture compliant with SLVS-EC version 2.0 specification, supporting data rate up to 10 Gbps...
541
5.5077
SLVS-EC 3.0 RX PHY (4nm)
The SLVS-EC Receiver PHY IP consists of a hard macro architecture compliant with SLVS-EC version 3.0 specification, supporting data rate up to 10 Gbps...
542
5.5077
DP 1.4 / eDP v1.4b TXPHY (14nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
543
5.5077
DP 1.4 / eDP v1.4b TXPHY (8nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
544
5.5077
DP 2.1a / eDP v2.0 RXPHY (4nm)
The DP/eDP RX PHY consists of hardmacro PHY compliant to DP v2.1a and eDP v2.0 specification, supporting maximum data rate of up to UHBR(20Gbps) opera...
545
5.5077
DP 2.1a / eDP v2.0 TXPHY (4nm)
The DP/eDP TX PHY consists of hardmacro PHY compliant to DP v2.1a and eDP v2.0 specification, supporting maximum data rate of up to UHBR(20Gbps) opera...
546
5.5077
DSC 1.2b Decoder
The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...
547
5.5077
DSC 1.2b Encoder
The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...
548
5.0
I2C Master Serial Interface Controller
The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...
549
5.0
I2C Master Serial Interface Controller
The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...
550
5.0
M31 DisplayPort RX IP in 6/7nm, 22nm
M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...
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