Design & Reuse
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1875 IP
551
8.0
PCIe 3.0/2.0 PHY
With sophisticated architecture and advanced technology, KNiulink PCIE GEN3/GEN2 PHY IP with PMA and PCS layer is designed for low power and high perf...
552
8.0
IGASERT08A, Derivative IP of IGPSERT12A Lane-based 1 - 12.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include 1GE, XAUI, RXAUI, XFI, 10GBase-KR...
553
8.0
Bi-directional High speed interface lane up to 12.5Gbps
InCirT offers SerDes which can deliver up to 12.5Gbps per lane for bidirectional data transfer. It consists of programmable receiver front-end and tra...
554
8.0
ARINC 429 IP Core
ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...
555
8.0
TSMC 12FFC Lane-based 1.25 - 22.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and a...
556
8.0
TSMC CLN5FF Glink 2.0 Die-to-Die PHY
IGAD2DY01A is a high speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions：Integrated Fan-Out (InFO) with RDL ...
557
8.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP deta...
558
8.0
TSMC N7FF 25.78125Gbps Enterprise SerDes
The receiver equalizes and recovers incoming serial data and de-serializes the data stream into selectable 32/40/64 bit-wide data bus. The transmitter...
559
7.0
MIPI C-PHY 8Gsps / D-PHY 9Gbps TRX Combo PHY (2nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
560
7.0
Display Controller - LCD / OLED Panels (AHB Bus)
The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD pane...
561
7.0
Display Controller - LCD / OLED Panels (AHB-Lite Bus)
The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to...
562
7.0
USB 2.0 Full/Low-Speed Device Core
The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality wit...
563
7.0
USB 2.0 Full/Low-Speed Embedded Host Controller
The FHG USB EHC is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 host functionality ...
564
7.0
USB 2.0 High/Full-Speed Device Core
The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functional...
565
7.0
USB 2.0 High/Full/Low-Speed Embedded Host Controller
The FHG USB2 EHC is a scalable, high performance IP-module for usage in ASIC and FPGA designs to integrate high/full/low-speed USB 2.0 host functional...
566
7.0
USB 2.0 OTG Full/Low-Speed Dual Role Core
The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host ...
567
7.0
USB 2.0 OTG High/Full/Low-Speed Dual Role Core
The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and ...
568
6.0
10/100 Mbit Ethernet MAC
The GRETH core implements 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. The core implements the 802.3-2002 Ethernet s...
569
6.0
32-bit PCI Bus Master/Target
32-bit PCI Bus Master/Target with configurable FIFOs and AHB back end...
570
6.0
I2C Master/Slave Controller Core IP
I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer...
571
6.0
RapidIO PHY
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the nee...
572
6.0
AHB To PCI Wrapper
VinChip’s AHB to PCI wrapper can be used to verify AHB (AMBA) based systems on a PCI environment for ease of debugging the target hardware and it can ...
573
6.0
Highly configurable high-speed serial link controller
The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement: * SpaceFibre controller (GRSPFI) * W...
574
6.0
Mil-Std-1553B/AS15531 Interface
The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus ...
575
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
576
6.0
MIPI Rx D-PHY
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577
6.0
Embedded Host Controller 1. 1
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578
6.0
Embedded Host Controller 2.0
...
579
6.0
Spacewire Codec with AHB host interface
The GRSPW core implements a Spacewire Codec with RMAP support and AMBA host interface. The core implements the Spacewire standard with the protocol id...
580
6.0
USB 1.1 Hub Controller
...
581
6.0
USB 1.1 Open Host Controller
...
582
6.0
USB 2.0 Device Controller
The Universal Serial Bus Device Controller provides a USB 2.0 function interface accessible from an AMBA-AHB bus interface. The core must be connected...
583
6.0
USB 2.0 Device Controller (IF Certified)
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584
6.0
USB 2.0 Host Controller
The USB 2.0 Host Controller core (GRUSBHC) provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller suppor...
585
6.0
USB 2.0 Host Controller (EHCI)
...
586
6.0
USB 2.0 PHY; SMIC 40nm LL
...
587
6.0
USB 2.0 PHY; SMIC 55nm LL
...
588
6.0
USB 3.0 Device
A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of...
589
6.0
USB based High Speed System Debug IP
Architecture Independent Design Supports any AMBA AHB based System Easily portable to other buses such as Avalon Standard USB 2.0 interface to th...
590
6.0
USB2.0 On-The-Go
VinChip’s USB 2.0 High Speed OTG controller is designed for flexibility and ease of use and facilitates implementation of a wide variety of applicatio...
591
6.0
AXI- Interconnect : Advanced Extensible Interface Bus IP
The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-...
592
5.0
I2C Master Serial Interface Controller
The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...
593
5.0
I2C Master Serial Interface Controller
The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...
594
5.0
I3C - DI3CM-HCI - MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improve...
595
5.0
UART Serial Interface Controller
The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller. The UART core can be efficiently implemented on FPGA and ASIC ...
596
5.0
SAS 4 Port 12G Recorder
The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications. Simple interface guarantees fast time to marke...
597
5.0
SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...
598
5.0
SATA PHY
Gigacom's VSL340 PHY is suitable for both Host and Device applications within a Serial ATA system. The VSL340 PHY operates to the Serial ATA specifica...
599
5.0
SATA/SAS 3.0 PHY
With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high pe...
600
5.0
PCIe Gen3 PHY
* Endpoint or Root Complex * PCIe standard multi-lane interface * PCIe power savings modes * Port bifurcation support...