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1875 IP
751
2.5
SATA Device on Virtex 6
The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...
752
2.5
SATA HOST 3 ON KINTEX 7 Ultrascale
The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale speed grade 2 FPGA. The...
753
2.5
SATA HOST 3 ON VIRTEX 7 GTH
...
754
2.5
SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...
755
2.5
SATA Host Controller
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...
756
2.5
SATA HOST Controller on Cyclone IV GX
The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...
757
2.5
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...
758
2.5
SATA Host controller on Virtex 5 FXT
The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
759
2.5
SATA Host Controller on Virtex 6 LXT
The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...
760
2.5
SATA Host on Altera Arria II GX
The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...
761
2.5
SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 H...
762
2.5
SATA HOST Synchronous IP
The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
763
2.5
SATA III HOST Controller on Virtex 6
The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The LDS SATA 3 ...
764
2.5
SATA RECORDER ON VIRTEX 6
The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of ...
765
2.5
SATA RECORDER ON VIRTEX 7 GTX
...
766
2.5
LDS SATA RECORDER IP ON ARTIX 7
...
767
2.5
LDS SATA RECORDER ON KINTEX 7
...
768
2.5
LDS SATA RECORDER ON ZYNQ
...
769
2.5
Serial ATA Dual Host Controller
The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5...
770
2.5
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...
771
2.5
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SA...
772
2.5
Dual SATA Host controller on Virtex 5 FXT FPGA
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5...
773
2.5
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed gr...
774
2.0
I2C Master Serial Interface Controller
Master serial interface compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be c...
775
2.0
I2C Slave Serial Interface Controller
Slave serial interface compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your FPGA, CPLD or ASIC device. A...
776
2.0
I3C Master / Slave Controller - MIPI Basic v1.0
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC ...
777
2.0
Advanced Encryption Standard (AES-128) core with AMBA AHB interface
The GRAES core implements the Advanced Encryption Standard (AES) symmetric encryption algorithm for high throughput application (like audio or video s...
778
2.0
Bi-directional AMBA AHB/AHB bridge
The bi-directional AHB/AHB Bridge is used to interconnect high-speed and low-speed AMBA AHB buses. The bridge supports synchronous clocks with any fre...
779
2.0
MIPI D-PHY UMC 65LL
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
780
2.0
MIPI D-PHY - UMC 55eHV
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
781
2.0
MIPI D-PHY Digital Front-End for FPGA
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
782
2.0
MIPI D-PHY Global Foundries 65LPe
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
783
2.0
MIPI D-PHY SMIC 40nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
784
2.0
MIPI D-PHY TSMC 40LP eDRAM
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
785
2.0
MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
786
2.0
MIPI M-PHY - UMC 40nm
MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY config...
787
2.0
Elliptic Curve Cryptography (ECC) core with AMBA APB interface
The GRECC core implements Elliptic Curve Cryptography (ECC) which is used as a public key mechanism and is well suited for application in mobile commu...
788
2.0
AMBA interface for Actel MIL-STD-1553B Cores
The GR1553 is a set of AMBA AHB/APB wrappers for the Actel AX/RTAX MIL-STD-1553B cores. Wrappers for the following Actel cores are provided: Core1553B...
789
2.0
Uni-directional AMBA AHB to AHB bridge
The Uni-directional AHB to AHB bridge is used to connect two AHB buses clocked by synchronous clocks with any frequency ratio. The bridge is connected...
790
2.0
Super Speed USB 3.0 Extensible Host Controller xHCI
...
791
1.0
V-By-One PHY & Controller (Tx+ Rx)
INNOSILICON™ VBO IP is designed for transmitting or receiving video signals between a video source device and display device, The IP is fully complian...
792
1.0
V-By-One Receiver_8ch
Innosilicon VBO RX IP is designed to receive and recover the video data from a VBO source device for display applications. Innosilicon VBO RX IP is c...
793
1.0
10G Multi-SerDes PHY
The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...
794
1.0
12.5G Multi-SerDes PHY
The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...
795
1.0
I2C Bus Interface
The serial controller interface (Single Master) core uses a two-wire bus for communicating between integrated circuits or standard peripherals like sm...
796
1.0
I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a t...
797
1.0
I2C Master and Slave
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for app...
798
1.0
32G Multi-SerDes For PCIe5.0/USB3.x PHY
The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...
799
1.0
32G Multi-SerDes PHY + Controller
The INNOSILICON™ 32G Multi-SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed ...
800
1.0
I3C
INNOSILICON™ I3C IP is fully compatible with the MIPI I3C and JESD403-1B standard and backward compatible to I2C. It enhances the existing I2C IP by n...
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