Design & Reuse
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1867 IP
1651
0.0
Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) ...
1652
0.0
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...
1653
0.0
Display Port Receiver IP
Display Port Receiver core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to a w...
1654
0.0
Display Port Transmitter IP
Display Port Transmitter core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to ...
1655
0.0
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...
1656
0.0
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC
The capacity of the Display Port 1.4 Rx IP Channel is supported. Up to 5.4bps per channel (HBR2), programmable analogue parameters like CDR Bandwidth,...
1657
0.0
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP
The Display Port 1.4 Rx IP Channel's maximum capacity is supported. Programmable analogue parameters including CDR Bandwidth, Equalizer Strength, Term...
1658
0.0
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
The maximum capacity of the Display Port 1.4 Rx IP Channel is supported. Up to 5.4bps per channel, programmable analogue settings such as CDR Bandwidt...
1659
0.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). built-in equalizer with programmable analogu...
1660
0.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2). Integrated 100-ohm termination resistors, a bu...
1661
0.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). built-in equalizer with programmable analogu...
1662
0.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2). programmable analogue fea...
1663
0.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP
The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2). Common-mode biassing of the CDR bandw...
1664
0.0
BitBLT Graphics Hardware Accelerator (AXI4 Bus)
The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...
1665
0.0
Mixel, Inc.- Mixed-signal IP
Mixel is focused on providing intellectual property cores and design services in the mixed-signal IC area. Mission Statement Provide our custom...
1666
0.0
GLink AXI Wrapper
GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface and provide data bus ...
1667
0.0
GLink CXS-Bridge
GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer and provides AMBA CXS...
1668
0.0
GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...
1669
0.0
GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...
1670
0.0
Globalfoundries 12nm MIPI D-PHY Rx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Recieve (Rx) only for Globalfoundries 12nm FinFET process nodes. Arasan's standalone D-PHY Rx only for...
1671
0.0
Globalfoundries 12nm MIPI D-PHY Tx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Transmit only for Globalfoundries 12nm FinFET process nodes. Arasan's standalone D-PHY Tx only for Glo...
1672
0.0
Globalfoundries 22nm MIPI D-PHY Rx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Recieve (Rx) only for Globalfoundries 22nm FinFET process nodes. Arasan's standalone D-PHY Rx only for...
1673
0.0
Globalfoundries 22nm MIPI D-PHY Rx only V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 Rx IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is av...
1674
0.0
Globalfoundries 22nm MIPI D-PHY Tx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Transmit only for Globalfoundries 22nm FinFET process nodes. Arasan's standalone D-PHY Tx only for Glo...
1675
0.0
Globalfoundries 22nm MIPI D-PHY Tx only V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 Tx IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is av...
1676
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is avail...
1677
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.2 @ 2.5GHz
Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 22nm FinFET process nodes. Arasan's D-PHY Global Foun...
1678
0.0
DMA AXI4-Stream Interface to AXI Memory Map Address Space
Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Mem...
1679
0.0
Small area rail clamp for FinFET
Power clamp ESD solutions Rail clamp ESD protection 0.75V domain Small area...
1680
0.0
Smart Network-on-Chip (NoC) IP
AI-Enhanced Automation for Smarter SoC Design FlexGen™ by Arteris redefines how SoC designers create Network-on-Chip IP by introducing cutting-edge...
1681
0.0
AMBA AHB 4 Channel DMA Controller
The DMA is a multiple-channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and F...
1682
0.0
AMBA AHB Address Trapper
The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus. This gives added visibility to the software in order...
1683
0.0
AMBA AHB Device/Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge supports Hos...
1684
0.0
AMBA AHB Simple Master Bridge
The Veriest AMBA AHB Simple Master Bridge Design IP provides a bridge between the embedded AMBA AHB bus master and a simplified generic local bus. The...
1685
0.0
AMBA AHB Slave to Local Interface Bridge
The Veriest AMBA AHB Slave Bridge Design IP offers a simple solution to provide a bridge between the embedded AMBA AHB bus and a simplified generic lo...
1686
0.0
AMBA AHB to APB Bus Bridge Core
The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...
1687
0.0
AMBA AXI Data Prefetch Buffer
The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM...
1688
0.0
AMBA AXI Data Writer Spreader
The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data ma...
1689
0.0
AMBA AXI Performance Monitor
The Veriest AMBA AXI Performance Monitor Design IP provides a mechanism for analysis of embedded AMBA AXI fabric latency. This gives added visibility ...
1690
0.0
ONFI 2.3 NAND Flash Controller
The Arasan ONFI 2.3 NAND Flash Controller IP Core is a full featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA developm...
1691
0.0
INTC IP
Interrupt Controller interface provides full support for programmable edge triggered (rising, falling) or sensitive, compatible with Interrupt Control...
1692
0.0
Interlaken IP
Interlaken interface provides full support for the Interlaken synchronous serial interface, compatible with Interlaken version 1.2 specification. Thro...
1693
0.0
Internal Synchronous SRAM Controller Core
The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...
1694
0.0
Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
Rambus CXL 2.0 Controller with AXI is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. Rambu...
1695
0.0
Low Power Dual PHY for UCIe low cost robust Chiplets
YorChip UniPHY™ Dual PHY is a flexible version of YorChip’s multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY’s unique feature ...
1696
0.0
DP/eDP PHY + Controller
INNOSILICON™ DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is f...
1697
0.0
APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...
1698
0.0
APB I2C master and slave
The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB sla...
1699
0.0
APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer
The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 613 V7.9.0 (2011-03) MAC Layer....
1700
0.0
APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-S...