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1875 IP
1801
0.0
USB2 - DUSB2 - USB 2.0 Device Controller
The DUSB2 is hardware implementation of full/high-speed peripheral controller that interfaces to the UTMI bus transceiver. The DUSB2 contains the USB ...
1802
0.0
USB2 - DUSB2-ULPI - USB 2.0 Device Controller with ULPI interface
The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI cont...
1803
0.0
USB2.0 OTG IP
This IP is developed as the USB2.0 OTG PHY. This PHY consists of an analog PHY and a PCS layer. The PCS section includes basic encoding and decoding a...
1804
0.0
USB2.0 OTG PHY in SMIC 0.11G
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1805
0.0
USB2.0 OTG PHY in SMIC 0.13EF
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1806
0.0
USB2.0 OTG PHY in SMIC 0.13G
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1807
0.0
USB2.0 OTG PHY in SMIC 28HKC+
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1808
0.0
USB2.0 OTG PHY in SMIC 28HKD 0.9/1.8V
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1809
0.0
USB2.0 OTG PHY in SMIC 28HKD 0.9/2.5V
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1810
0.0
USB2.0 OTG PHY in SMIC 40NEF
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1811
0.0
USB2.0 OTG PHY in SMIC 40NLL
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1812
0.0
USB2.0 OTG PHY in SMIC 55EF
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1813
0.0
USB2.0 OTG PHY in SMIC 55NLL
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1814
0.0
USB2.0/eUSB2.0 PHY & Controller
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications. Innosilicon provides a comprehensive se...
1815
0.0
USB3.x Host IP
USB3.x Host interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its US...
1816
0.0
USB4 PHY - SS SF2, North/South Poly Orientation
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
1817
0.0
USB4 PHY IP for TSMC N3E
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
1818
0.0
DSC 1.2b Decoder
The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...
1819
0.0
DSC 1.2b Encoder
The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...
1820
0.0
ASIL-B Ready ISO 26262 Certified VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
1821
0.0
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to ...
1822
0.0
TSMC CLN12FFC Lane-based 1.5 - 16 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4,SAS-3 G1-G4, SATA-...
1823
0.0
TSMC CLN28HPC+ Derivative IP of IGASERT06A Enterprise Multi-Standard SerDes
The GUC's Quad-Lane EMS-XT PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include CEI-28G-VSR, CEI-25G...
1824
0.0
TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
IGPD2DZO1A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions, Integrated Fan-Out (InFO) with the ...
1825
0.0
TSMC CLN5FF GLink 2.0 Die-to-Die PHY
IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL ...
1826
0.0
TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL...
1827
0.0
TSMC CLN5FF GLink GPIO
IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initiali...
1828
0.0
TSMC CLN5FF GLink-3D Die-to-Die Master PHY
IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY. It is used to transmit data between dies and assembled using TSMC System on Integ...
1829
0.0
TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY. It is used to transmit data between dies and assembled using TSMC System on Integr...
1830
0.0
TSMC CLN7FF Lane-based 1.5 – 22.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and a...
1831
0.0
ISO 7816 based digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
Smart card controller core is compliant to ISO 7816 3 specification. The core is a technology independent, fully synchronous design. The controller fu...
1832
0.0
ISO 7816 based Smart Card Reader IP
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...
1833
0.0
eSPI & SPI Master Controller w/FIFO
The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...
1834
0.0
eSPI & SPI Slave Controller w/FIFO
The Digital Blocks DB-eSPI-SPI-S-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...
1835
0.0
XSR PHY for TSMC N5
The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip m...
1836
0.0
HSSTP Link
The High-Speed Serial Trace Port (HSSTP) Controller IP implements the ARM HSSTP protocol. HSSTP replaces the existing parallel data output port, enab...
1837
0.0
HSSTP PHY TX 5nm (1.5 Gbps, 3 Gbps, and 6 Gbps)
The HSSTP TX PHY is a 5nm hard macro supporting up to 6Gbps data rates with dual lanes and a hybrid mode driver for AC-coupled links. It includes feat...
1838
0.0
Multi-Function PCI Master/Target Interface Core
The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...
1839
0.0
Multiprotocol 10G PHY in TSMC (16nm, N7)
The multi-lane Synopsys IP Multi-Protocol 10G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio, meeting the growing need...
1840
0.0
eUSB 2.0 PHY for TSMC N3A
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1841
0.0
eUSB 2.0 PHY in TSMC (N3A) for Automotive
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1842
0.0
eUSB2V2 PHY
Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals,...
1843
0.0
eUSB2V2 PHY in TSMC (22nm)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1844
0.0
LVDS Tx IP, Silicon Proven SMIC 14SF+
The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer for Video interface and...
1845
0.0
LVDS/TTL PHY & Controller
INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...
1846
0.0
NVM Express (NVMe) Controller (compliant with NVMe 1.4 Base Specification)
The NVM Express (NVMe) controller is compliant with NVMe 1.4 Base Specification. Most of NVMe feature supported to achieve well compatibility, SRIOV i...
1847
0.0
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...
1848
0.0
AXI Bridge for PCIe IP Core
The AXI Bridge for PCIe IP core is the  IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.The AXI Bridge IP c...
1849
0.0
AXI External Memory Controller
The AXI External Bus Interface (EBI) allows the processor to transmit and receive data to an external device, usually a memory (SRAM, Flash, etc.). Th...
1850
0.0
AXI Interconnect Fabric
The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...