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1875 IP
1851
0.0
AXI Interface Core
Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and rea...
1852
0.0
AXI Multilayer Interconnect
The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...
1853
0.0
AXI Performance Subsystem
The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance. ...
1854
0.0
AXI Subsystem
The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...
1855
0.0
AXI to AHB Lite Bus Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
1856
0.0
AXI to APB Bridge
The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...
1857
0.0
AXI to APB Bus Bridge
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...
1858
0.0
AXI4 Memory Map to AXI4-Stream Bridge
Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...
1859
0.0
CXL 2.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1860
0.0
CXL 3 Controller
The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for...
1861
0.0
CXL 3 Controller
The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for...
1862
0.0
CXL 3.0 Device Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1863
0.0
CXL 3.0 Dual Mode Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1864
0.0
CXL 3.0 Host Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1865
0.0
CXL 3.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1866
0.0
CXL Controller IP
The CXL Controller IIP core supports the CXL 1.0 and 1.1 Specification. Through its CXL compatibility, it provides a simple interface to a wide range ...
1867
0.0
CXP Device IP
CXP Device core is compliant with standard CXP specification as 1.1/1.1.1/2.0. Through its compatibility, it provides a simple interface to a wide ran...
1868
0.0
CXP Host IP
CXP Host core is compliant with standard CXP 1.1/1.1.1/2.0 specification. Through its compatibility, it provides a simple interface to a wide range of...
1869
0.0
Synopsys 32G PHY NCS for TSMC N5
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
1870
0.0
Synopsys Auto-Grade MIPI D-PHY Tx for TSMC N7
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
1871
0.0
Synopsys MIPI C-PHY IP on TSMC N7
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1872
0.0
Synopsys MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes for TSMC N5
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1873
0.0
Synopsys PCIe 4.0 PHY IP for TSMC N7
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
1874
0.0
Synopsys PCIe 5.0 PHY IP for SF5
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
1875
0.0
Synopsys USB4 PHY IP for TSMC N4P
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
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