Design & Reuse
arrow AMBA AHB / APB/ AXI (192)
arrow CXL (18)
arrow D2D (58)
arrow Gen-Z (6)
arrow HDMI (83)
arrow I2C (98)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (460)
arrow Multi-Protocol PHY (37)
arrow PCI (254)
arrow RapidIO (6)
arrow SAS (6)
arrow SATA (95)
arrow Smart Card (6)
arrow USB (390)
arrow V-by-One (22)
arrow VESA (73)
arrow Other (66)
1875 IP
401
10.0
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
The CL12822M4R2JM2LIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12822M4...
402
10.0
SATA 3 PHY
Gigacom's VSL340A PHY updated version of VSL340 to support SATA3 and backward compatible with SATA 1 and 2. VSL340A is suitable for both Host and Devi...
403
10.0
PCI Express - Configurable PCI Express 4.0 IP
The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification". This IP supports the major functi...
404
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
405
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
406
10.0
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
407
10.0
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
408
10.0
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
409
10.0
PCIe 4.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...
410
10.0
PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
411
10.0
PCIe 5.0 PHY NCS in TSMC (N7, N6, N5, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
412
10.0
UCIe D2D Adapter
The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer a...
413
10.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
414
10.0
PCIe Gen2 PHY
* Endpoint or Root Complex * PIPE includes skip insertion, deletion * PCIe power savings modes * Port bifurcation support...
415
10.0
PCIe/HCSL Differential IO Buffer - TSMC 16FFC
Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...
416
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
417
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
418
10.0
PCIe3 SSCG PLL - TSMC 12FFC
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
419
10.0
PCIe3 SSCG PLL - TSMC 16FFC
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
420
10.0
PCIe4 Ethernet SERDES PHY - TSMC N5
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
421
10.0
PCIe5 Ref Clock SSCG PLL - TSMC 6FF
Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...
422
10.0
HDMI1.4 RX LINK
Silicon Library's HDMI1.4b RX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
423
10.0
HDMI1.4 TX LINK
Silicon Library's HDMI1.4b TX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
424
10.0
HDMI2.0 RX LINK
Silicon Library's HDMI2.0 RX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
425
10.0
HDMI2.0 TX LINK
Silicon Library's HDMI2.0 TX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
426
10.0
SerDes Hard Macro-IP in GlobalFoundries 22FDX
Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture, Support for multiple protocols, as well a...
427
10.0
VESA DSC Encoder and Decoder IP Solutions
Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-definition displa...
428
10.0
UFS Host Controller IP
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
429
10.0
UFSHCI 4.0
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
430
10.0
AHB MultiMatrix Fabric
The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters. The off-the-self configu...
431
10.0
AHB Quad SPI Controller with Execute in Place
The Quad Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device. Reading and wri...
432
10.0
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and P...
433
10.0
Die-to-Die Controller IP
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...
434
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
435
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
436
10.0
Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale ...
437
10.0
High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
438
10.0
TileLink Target
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...
439
10.0
MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
The MXL-CPHY-CSI-2-TX+ is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supporting ...
440
10.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
441
10.0
MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP
The MXL-CDPHY-2L-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, sourcesynchronous, physical Layer supporting the MIPI Alliance Specificatio...
442
10.0
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 22ULP
The MXL-CDPHY-DSI-RX-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...
443
10.0
MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
The MXL-CPHY-DPHY-DSI-TX is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display in...
444
10.0
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 7 FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes. Users are able to configure this Combo PHY into either D-PHY or C-PHY mode to supp...
445
10.0
MIPI CSI-2 Receiver for FPGA
MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor....
446
10.0
MIPI CSI-2 Transmitter for FPGA
MIPI CSI-2 Tx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processer...
447
10.0
MIPI D-PHY CSI-2 TX (Transmitter) 2.5Gbps in TSMC 65LP
The MXL-DPHY-2p5G-CSI-2-TX-T-65LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...
448
10.0
MIPI D-PHY Receiver for TSMC 40nm LP
The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process....
449
10.0
MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI
The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process....
450
10.0
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of TSMC 40nm LP process....