Design & Reuse
arrow Cryptography (302)
arrow Data Integrity - Error Correction (4)
arrow Embedded Security Modules (18)
arrow MACsec, IPsec (30)
arrow Post-Quantum Solutions (25)
arrow PUF Based (24)
arrow Random Number Generator (RNG) (19)
arrow Root of Trust (17)
arrow Security Platform (32)
arrow Sensors & Monitors (21)
492 IP
151
9.0
TRNG fully compliant with NIST 800-22
The eSi-TRNG is a high quality implementation of a True Random Number Generator fully compliant with latest NIST 800-22. The block uses a standard AM...
152
8.0
HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface
This is a high performance, small footprint HASH IP Core. It supports three HASH algorithms: MD5, SHA1, SHA256. A S/G DMA engine keeps the core runni...
153
8.0
Secure Hash Algorithm-3 (SHA-3)
CYB-SHA3 implements Secure Hash Algorithm-3 (SHA-3) family of functions on binary data with the NIST FIPS 202 Standard. It supports cryptographic hash...
154
8.0
Secure-IC's Securyzr™ SM4-GCM Multi-Booster
The SM4-GCM Multi-Booster crypto engine is a scalable implementation of the SM4-GCM algorithm compliant with the standard GBT.32907-2016 published by ...
155
8.0
Secure-IC's Securyzr™ SM4-GCM Multi-Booster
The SM4-GCM Multi-Booster crypto engine is a scalable implementation of the SM4-GCM algorithm compliant with the standard GBT.32907-2016 published by ...
156
8.0
AES Encoder and Decoder
CYB-AES implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It supports all of the available ke...
157
8.0
AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.
This is a high performance, small footprint crypt/decrypt IP Core. It features up to 8 independent crypt engines. Three DMA engines make sure the cor...
158
8.0
SHA256 Encoder and Decoder
SHA256 is a Secure Hash Algorithms which is one of the latest hash functions standarized by the U.S Federal Government. SHA 256 IP Core Algorithm impl...
159
8.0
ZLIB compatible compression and decompession, with DMA and AXi interface
This is a high performance, small footprint ZLIB compatible IP Core. It features 3 DMA engines, AXI interconnect and separate clocks for AXI interface...
160
8.0
CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm
eSi-Dilithium is a hardware core for accelerating the high-level operations specified in the NIST FIPS 204 standard. Dilithium is an integral part o...
161
8.0
CRYSTALS Kyber core for accelerating NIST FIPS 203 Key Encapsulation Mechanism
eSi-Kyber is a hardware accelerator core designed to accelerate post-quantum Key Encapsulation Mechanism (KEM) as defined by NIST FIPS 203. Kyber, a...
162
7.0
MACsec 10G/25G
Comcores MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE...
163
7.0
Falcon IP Core
Falcon IP Core is a post-quantum digital signature algorithm (DSA). It is currently under development. It is going to be compliant with Falcon specifi...
164
7.0
ECDSA IP Core
ECDSA IP Cores perform digital signature generation and verification in compliance with the Elliptic Curve Digital Signature Algorithm (ECDSA) specifi...
165
7.0
AES GCM IP Core
AES GCM IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197"...
166
7.0
AES IP Core
AES IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197". Th...
167
7.0
SHA3 IP Core
SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'. This standard...
168
7.0
Dilithium IP Core
Dilithium IP Core is a post-quantum digital signature algorithm (DSA). It currently supports Sign and Verify functions, with key generation functional...
169
7.0
DRBG IP Core
DRBG IP Cores perform deterministic random bit generation in compliance with the standards and guidelines defined in 'NIST SP 800-90A'. This standard ...
170
7.0
TRNG IP Core
TRNG IP Cores perform true random number generation in compliance with the standards and guidelines defined in 'NIST SP 800-90B'. This standard specif...
171
7.0
RSA IP Core
RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm spec...
172
7.0
RSA Keygen IP Core
RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'. This standard specifie...
173
7.0
External NOR Flash Protection
PUFxip is the extension function available for PUFcc, extending the Hardware Root of Trust to protect critical assets in the NOR Flash. PUFxip can wid...
174
7.0
KYBER IP Core
Kyber IP is a core designed for Kyber post-quantum Key Encapsulation Mechanism (KEM). It currently supports the Encapsulation and Decapsulation functi...
175
6.0
External NAND Flash Protection
PUFenc is the extension function available for PUFcc, extending the Hardware Root of Trust to protect critical assets in the NAND Flash. PUFenc can wi...
176
5.0
256-bit SHA Cryptoprocessor Core
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for m...
177
5.0
Hardened 128-bit Advanced Encryption Standard (AES) coprocessor
The AES Coprocessor encrypts and decrypts 128-bit data blocks by computing an AES algorithm with a 128, 192 or 256-bit key through a highly secure arc...
178
5.0
Hardware accelerator for RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
The Public Key Cryptographic Coprocessor (PK2C) is a hardware accelerator intended to speed-up the core functions of public-key cryptography algorithm...
179
5.0
Hash Crypto Engine
The Hash Crypto Engine is flexible and optimized hash IP core compliant with FIPS 180-3 (HASH functions), FIPS 198 (HMAC function) and OSCCA (SM3). W...
180
5.0
Hash-based DRBG library compliant with the NIST SP 800-90A standard
The software Deterministic Random Bit Generator (DRBG) is a Hash-based library compliant with the NIST SP 800-90A standard....
181
5.0
KASUMI Crypto Engine
The KASUMI IP core is 3GPP confidentiality and integrity algorithms (UEA1/UIA1) stream cipher for telecommunication applications, requiring high perfo...
182
5.0
Java Card compliant cryptographic library for encryption and decryption of RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
The Public Key Cryptographic Library (PKCL) provides standardized key computation, encryption, decryption, signature and verification functionalities ...
183
5.0
DCRP1A - 100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
The CryptOne, a 100% secure cryptographic system, has been based on more than 20 years DCD’s market experience. Starting from 1999, Digital Core Desig...
184
5.0
Advanced Encryption Standard Module
The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...
185
5.0
Advanced Encryption Standard Module
The CC-AES-AXI is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...
186
5.0
Secure cryptographic library compliant with the X9.31 and FIPS 186-4 standards.
The Software RSA Key Generator is a secure cryptographic library compliant with the X9.31 and FIPS 186-4 standards....
187
5.0
Secure key computation, encryption, decryption, signature and verification functionalities compliant with the PKCS#1
The Software RSA library provides standardized key computation, encryption, decryption, signature and verification functionalities for all key sizes u...
188
5.0
Secure software implementation of SHA-1, SHA-2 and HMAC-SHA-256
The Software HMAC-SHA is a secure cryptographic library including SHA-1, SHA-2 and HMAC-SHA-256 implementations....
189
5.0
AES - DAES XTS - Cryptographic co-processor for lightweight cryptography
DAES XTS IP Core from Digital Core Design is a compact cryptographic co-processor designed to seamlessly implement the Rijndael encryption algorithm i...
190
5.0
DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor
The Triple DES Coprocessor is a Data Encryption Standard (FIPS 46-3) peripheral computing DES and Triple DES (TDES and 3DES) encryption and decryption...
191
5.0
AES-XTS Multi-Booster
The AES-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the AES algorithm making the solution suitable for a wide rang...
192
5.0
Device Secure Debug
The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary Scan Architecture. Giving a full access to the inte...
193
5.0
SHA - DSHA2-256 - SHA IP Core with native SHA2-256 HMAC support
The DSHA2-256 is a universal solution which efficiently accelerates SHA2-256 hash function compliant with FIPS PUB 180-4. It computes message digest i...
194
5.0
SHA-256 encryption and decryption coprocessor
The SHA-256 Coprocessor is a hardware implementation of the SHA-256 cryptographic hash function...
195
5.0
SHA-384 and SHA-512 Secure Hash Crypto Engine
The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash functions provisioned by t...
196
5.0
The True Random Number Generator (TRNG) Digital Noise Source is a standard-cell based entropy generator
​The True Random Number Generator (TRNG) Digital Noise Source is a standard-cell based entropy generator compliant with the statistical test of the FI...
197
5.0
High Throughput Elliptic Curve Cryptography hardware acceleration Core
eSi-ECDSA-HT is a High Throughput (HT) Elliptic Curve Cryptography (ECC) hardware acceleration core, which supports EC Digital Signature Algorithm (EC...
198
5.0
Elliptic Curve Digital Signature generation and verification
eSi-ECDSA is a hardware acceleration core for Elliptic Curve (EC) Digital Signature Algorithm modular arithmetic operations defined in IEEE1363 and ot...
199
5.0
SNOW3G Crypto Engine
The SNOW3G IP core is 3GPP confidentiality and integrity algorithms (UEA2/UIA2) stream cipher for telecommunication applications, requiring high perfo...
200
5.0
Integrated Secure Element (iSE)
As attacks become more sophisticated, connected electronic devices require more and more security. Because of this, FPGA and Systems On Chip are expec...