Security IP Core

The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...

252

3.0

Ultra-Compact Data Encryption Standard (DES/3DES) Core

The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....

253

3.0

SNOW 3G Encryption Core

The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...

254

3.0

True Random and Pseudorandom Number Generator

The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...

255

3.0

LRW-AES Core

Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...

256

3.0

LRW-AES Core

Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....

257

3.0

LRW-AES Core

LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...

258

3.0

Cryptographically Secure Pseudo Random number Generator IP Core

The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...

259

3.0

RSA Public Key Exponentiation Accelerator

Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The opera...

260

3.0

Pseudorandom Number Generator (PRNG) - Balanced variant

The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...

261

3.0

Pseudorandom Number Generator (PRNG) - High-speed variant

The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...

262

3.0

SSL/TLS Processor IP Core with an AXI Bus Interface

The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of...

263

3.0

XTS-AES IEEE P1619 Core Families

XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 fa...

264

2.0

GCM-AES Authenticated Encryption & Decryption

The AES-GCM128 core from Alma Technologies implements the GCM-AES authenticated encryption and decryption, as specified in the NIST SP800-38D recommen...

265

2.0

AES Encryption & Decryption with Programmable Block-Cipher Mode

The AES-P core from Alma Technologies implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks ...

266

2.0

AES IP Core

Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256). The AES...

267

2.0

SHA512 & SHA384 core

The eSi-SHA512 core is an easy to use SHA hash accelerator peripheral for both SHA512 and SHA384. This is a cryptographic hash function designed by t...

268

2.0

Clock Attack Monitor GlobalFoundries