Design & Reuse
5 IP
1
0.7246
HMC Memory Model
HMC Memory Model provides an smart way to verify the HMC component of a SOC or a ASIC. The SmartDV s HMC memory model is fully compliant with standard...
2
0.0
HMC2 Verification IP
Truechip's HMC Verification IP provides an effective & efficient way to verify the HMC components of an ASIC/FPGA or SoC i.e. Host or Device. Truechip...
3
0.0
Hybrid Memory Cube (HMC) Verification IP
HMC : Asiczen’s Verification IP for HMC provides a comprehensive set of protocol, methodology, verification and productivity features, enabling user t...
4
0.0
Hybrid Memory Cube Verification IP
Atria Logic Hybrid Memory Cube verification IP is a reusable, configurable verification component developed using SystemVerilog. The IP offers an easy...
5
0.0
Hybrid Memory Cube (HMC 2.0) VIP
HMC-Xactor is a comprehensive memory VIP solution portfolio for Hybrid Memory Cube (HMC 2.0) targeting a new standard in memory performance, density, ...