Design & Reuse
7 IP
1
0.7246
UART Verification IP
UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC. The SmartDV s UART Verification IP is fully compliant with...
2
0.0
Simulation VIP for UART
Best-in-class UART Verification IP for your IP, SoC and system-level design testing. In production since 2014 on dozens of production designs....
3
0.0
VC Verification IP for UART
Synopsys VC Verification IP (VIP) for UART provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...
4
0.0
UART (interface) eVC
The Universal Asynchronous Receiver Transmitter (UART) interface-level eVC is a powerful verification bundle built around the UART inteface industry s...
5
0.0
UART 16x50 eVC
The Universal Asynchronous Receiver Transmitter (UART) 16x50 device-level eVC is a powerful verification bundle built around the UART 16x50 class of d...
6
0.0
UART eVC - Fully documented, of the shelf component for Verisity's Specmean Elite functional verification environment
Silicon Interfaces’ UART eVC is a fully documented, off the shelf component for Verisity’s Specman EliteTM functional verification environment. At the...
7
0.0
UART VMM based Verification IP
The VMM based UART VIP is complaint to National Semiconductor 16550 design. The UART interface allows a duplex, asynchronous, serial communication and...