1 10.0

DesignWare Library contains the essential infrastructure IP for design and verification The DesignWare Library contains the essential infrastructure IP for design and verification including datapath components, AMBA On-Chip Bus and microc...

2 0.7246

Display port 2.0 VIP Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other ...

3 0.7246

OpenCAPI VIP The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces. It includes an e...

4 0.7246

TileLink VIP TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC. The SmartDV s TileLink Verification IP is fully co...

5 0.0

Mem Test Analyzer Core The Rambus Mem Test Analyzer Core from Rambus is used to capture the results from Rambus Memory Test Core. The Mem Test Analyzer Core can be used in ...

6 0.0

cjTAG IEEE 1149.7 Compact TAP Controller The IEEE 1149.7 Compact TAP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantage of IEEE 1149.7 featu...

7 0.0

cjTAG IEEE 1149.7 DTS Adapter The DTS Adapter from Silvaco enables an existing IEEE 1149.1 debug test system (DTS) to take advantage of the advanced debug/test capabilities availab...

8 0.0

Path Margin Monitor IP The Path Margin Monitor (PMM) solution consists of multiple PMM units, a PMM controller, and associated software & EDA automation. PMM IP is a buildin...

9 0.0

STAR Memory System (SMS) Test & Repair IP Synopsys SLM SMS IP is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or non-repairable embedded memories ...

10 0.0

STAR Memory System (SMS) Test & Repair IP for CAMs (Content Addressable Memories) Synopsys SLM SMS CAM 6 IP can be used to perform Test, Repair and Diagnostics for Content Addressable Memories such as BCAM, TCAM, XYCAM...

11 0.0

STAR Hierarchical System (SHS) IP Synopsys SLM STAR Hierarchical System (SHS) is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores...

12 0.0

DEV - Virtual Platform Development and Simulation The Imperas Developer products consist of tools, models and infrastructure components critical for the high quality, rapid development and verificatio...

13 0.0

M*SDK - Advanced Multicore Software Development Kit The focus of the Imperas products is to save engineering time in the development of embedded software, primarily achieved by making the engineering pr...

14 0.0

QuantumLeap - Virtual Platform Simulation Acceleration QuantumLeap is a parallel simulation performance accelerator that leverages a new synchronization algorithm to provide the fastest virtual platform so...

15 0.0

ISS - The Imperas Instruction Set Simulator Instruction Set Simulator (ISS) - fast, simple, easy to use, cross software development for embedded systems The Imperas ISS is often the first simul...

16 0.0

DVinsight - Correct by construction SV UVM code with a smart editor DVinsight™ is a smart editor for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code.DV...

17 0.0

Symphony Mixed-Signal Platform The industry s fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across A/D...

18 0.0

Tessent Embedded SDK The Tessent Embedded Software Development Kit (ESDK) is a set of software libraries designed to be compiled and run on an embedded system within an So...

19 0.0

Analog FastSPICE Platform Foundry-certified, the AFS Platform delivers nm SPICE accuracy >5x faster than traditional SPICE and >2x faster than parallel SPICE simulators. Offeri...

20 0.0

SimXACT - Gate Simulation Productivity and Analysis Technology Gate-Level X-Verification : Reduce Bring-up Time...

21 0.0

SimAccel FPGA-Accelerated Verification Accelerate RTL Verification and SW Bring-up Target IPs and SoCs NVMe controller PCIe RC/EP IP, Repeater, Switch Flash controller AMBA NoCs and periphe...

22 0.0

SimCluster GLS Gate-Level Parallel Simulation : Reduce Time to Simulation Sign-off...

23 0.0

NVMe-Xactor VIP Solution NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and ...

24 0.0

SD Express Card Verification IP Truechip's SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of...

25 0.0

VC Functional Safety Manager VC Functional Safety Manager provides a comprehensive tool for IP and semiconductor groups targeting functional safety certification for ISO 26262, IE...

26 0.0

Side Channel Studio Side-Channel Attacks (SCA) extract cryptographic keys from hardware systems by analyzing power traces or electromagnetic emission data from the target...

27 0.0

Fault Injection Studio Fault Injection Attacks (FIA) extract secrets, e.g. cryptographic keys, from hardware systems by injecting faults, e.g. using a laser beam to disrupt ...

28 0.0

Cogita-PRO Cogita-PRO is AI-based verification analytics and debugging solutionPredictable and faster verification convergenceCogita-PRO enables engineers to pre...

29 0.0

Performance modeling using stochastic components Evaluate The System Architecture And Generate Latency/Throughput Graphs. In stochastic modeling, different channels need to be modeled for each input-...

30 0.0

Multi-domain simulation at the system-level for mixed signal behavior modeling The simulators implement various models of computation. Most of these models of computation can be viewed as a framework for component-based design, w...