Design & Reuse
Catalog of SIP Cores
System on Chip design resources

PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface

KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and P...