Design & Reuse
Catalog of SIP Cores
System on Chip design resources

PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support

Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controlle...