Design & Reuse
Catalog of SIP Cores
System on Chip design resources

Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO

The Digital Blocks DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or an...