TSMC's new A14 process is already backed by certified EDA tools from Cadence, Synopsys, and Siemens to accelerate next-gen AI and chiplet-based designs.
allaboutcircuits.com, May. 07, 2025 –
At its recent North America Technology Symposium, TSMC unveiled its next-generation A14 process technology—an ambitious leap beyond the soon-to-be-deployed N2 node. Hot on the heels of this announcement, several EDA companies publicly declared support for the A14 platform, aligning their tools and flows with the foundry’s future-facing roadmap.
Expected to enter production in 2028, A14 builds on the nanosheet foundation laid by the N2 process. The upgrade delivers up to 15% speed improvement or 30% power reduction at equivalent performance, along with a 20% logic density boost. TSMC has also introduced its NanoFlex Pro standard cell architecture, enhancing design flexibility and pushing the limits of AI acceleration, mobile computing, and edge innovation.
| Features | A14 (1.4 nm) |
| Production Date | 2028 |
| Transistor Architecture | Gen 2 GAAFET, Nanoflex Pro |
| Performance | +15% than N2 |
| Power Consumption | -30% than N2 |
| Logic Density | +20% than N2 |
| Packaging | Larger-scale integration than N2 |
Beyond the transistor, TSMC’s roadmap broadens to advanced packaging with chip-on-wafer-on-substrate (CoWoS), its compact universal photonic engine (COUPE), and high-bandwidth memory support. These additions are not peripheral; they’re foundational to realizing the chiplet-based, multi-die architectures that define AI-era compute platforms.
Cadence, Synopsys, and Siemens are among the early adopters certifying tools for A14 while extending robust support across existing platforms like A16, N2P, and 3DFabric.
Cadence’s collaboration with TSMC now spans digital, analog, and thermal analysis tools certified for both N2P and A16. The company's A14 work is already underway, building on pre-silicon DDR5 IP, UCIe-compatible chiplet interfaces, and 3Dblox-enabled 3DIC flows. Cadence is also advancing CoWoS-L support, tailored for AI workloads with HBM3E integration and feedthrough-aware planning.