www.newelectronics.co.uk, May. 21, 2025 –
Keeping pace with Moore’s law continues to be challenging and is driving adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices.
These packaging technologies disaggregate what would typically be a homogenous, monolithic device, like an ASIC or SoC, into discrete, unpackaged dies, known as chiplets, specically designed and optimised for operation within a package in conjunction with other chiplets. This is also referred to as heterogenous integration (HI), where multiple dies or chiplets are integrated into a system-in-package (SiP) design. Menu Heterogeneously integrated SiP devices offer considerable benets, including higher performance, lower power usage, smaller area, lower cost, and faster time to market. However, thus far they are designed and produced by only a small number of advanced users. Broad industry proliferation will require standardisation of chiplet models and die-to-die connectivity IP - efforts currently underway - supported by new workows.
In this article we will focus on ve workows that are essential for planning, implementing, verifying, and co-designing heterogenous designs.
Architectural planning and analysis
Physical design planning and analysis
Design analysis
Reliability analysis
Test planning and validation
As a design moves through the ve workows, it also undergoes modelling and analysis to continuously qualify that the design meets its performance specications. Predictive modelling is applied during the architectural and physical design planning phases, with the primary goal of qualifying engineering decisions and gaining insight into downstream performance. This also enables team members to validate that they are selecting the right packaging and system architecture to best address the problems they are trying to solve. In-design modelling further qualies a design as more content and details become available during implementation. The objective is to identify and resolve issues while corrective action is still relatively easy and inexpensive. These issues are typically related to power, thermal, signal integrity, process rules, or even mechanical integration. The last step is nal signoff of the completed design prior to release to manufacturing. Because HI designs include a wide range of multi-domain design content and IP, comprehensive data management support throughout all ve workows is required.